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CY7C0837AV-133BBC PDF预览

CY7C0837AV-133BBC

更新时间： 2024-11-07 03:08:23
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
28页 821K
描述
FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18 Synchronous Dual-Port RAM

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CY7C0837AV-133BBC 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：BGA包装说明：13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
针数：144Reach Compliance Code：not_compliant
ECCN代码：3A991.B.2.BHTS代码：8542.32.00.41
风险等级：5.88最长访问时间：4 ns
其他特性：PIPELINED ARCHITECTUREI/O 类型：COMMON
JESD-30 代码：S-PBGA-B144JESD-609代码：e0
长度：13 mm内存密度：589824 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：18
功能数量：1端口数量：2
端子数量：144字数：32768 words
字数代码：32000工作模式：SYNCHRONOUS
最高工作温度：70 °C最低工作温度：
组织：32KX18输出特性：3-STATE
封装主体材料：PLASTIC/EPOXY封装代码：LBGA
封装等效代码：BGA144,12X12,40封装形状：SQUARE
封装形式：GRID ARRAY, LOW PROFILE并行/串行：PARALLEL
峰值回流温度（摄氏度）：240电源：3.3 V
认证状态：Not Qualified座面最大高度：1.6 mm
最大待机电流：0.075 A最小待机电流：3.14 V
子类别：SRAMs最大压摆率：0.3 mA
最大供电电压 (Vsup)：3.465 V最小供电电压 (Vsup)：3.135 V
标称供电电压 (Vsup)：3.3 V表面贴装：YES
技术：CMOS温度等级：COMMERCIAL
端子面层：TIN LEAD端子形式：BALL
端子节距：1 mm端子位置：BOTTOM
处于峰值回流温度下的最长时间：30宽度：13 mm
Base Number Matches：1

CY7C0837AV-133BBC 数据手册

 浏览型号CY7C0837AV-133BBC的Datasheet PDF文件第2页浏览型号CY7C0837AV-133BBC的Datasheet PDF文件第3页浏览型号CY7C0837AV-133BBC的Datasheet PDF文件第4页浏览型号CY7C0837AV-133BBC的Datasheet PDF文件第5页浏览型号CY7C0837AV-133BBC的Datasheet PDF文件第6页浏览型号CY7C0837AV-133BBC的Datasheet PDF文件第7页 
CY7C093794V CY7C093894V CY7C09289V CY7C09369V CY7C09379V CY7C09389VFLEx18™ 3.3V 64K/128K  
x 36 and 128K/256K x 18  
Synchronous Dual-Port RAM  
CY7C0837AV  
CY7C0830AV/CY7C0831AV  
CY7C0832AV/CY7C0833AV  
FLEx18™3.3V64K/128Kx36and128K/256Kx18  
Synchronous Dual-Port RAM  
Functional Description  
Features  
• True dual-ported memory cells that allow simultaneous  
The FLEx18™ family includes 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit  
and 9-Mbit pipelined, synchronous, true dual-port static RAMs  
that are high-speed, low-power 3.3V CMOS. Two ports are  
provided, permitting independent, simultaneous access to any  
location in memory. The result of writing to the same location  
by more than one port at the same time is undefined. Registers  
on control, address, and data lines allow for minimal set-up  
and hold time.  
During a Read operation, data is registered for decreased  
cycle time. Each port contains a burst counter on the input  
address register. After externally loading the counter with the  
initial address, the counter will increment the address inter-  
nally (more details to follow). The internal Write pulse width is  
independent of the duration of the R/W input signal. The  
internal Write pulse is self-timed to allow the shortest possible  
cycle times.  
A HIGH on CE0 or LOW on CE1 for one clock cycle will power  
down the internal circuitry to reduce the static power  
consumption. One cycle with chip enables asserted is required  
to reactivate the outputs.  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap-around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
access of the same memory location  
• Synchronous pipelined operation  
• Family of 512-Kbit, 1-Mbit, 2-Mbit, 4-Mbit and 9-Mbit  
devices  
• Pipelined output mode allows fast operation  
• 0.18-micron CMOS for optimum speed and power  
• High-speed clock to data access  
• 3.3V low power  
— Active as low as 225 mA (typ)  
— Standby as low as 55 mA (typ)  
• Mailbox function for message passing  
• Global master reset  
• Separate byte enables on both ports  
• Commercial and industrial temperature ranges  
• IEEE 1149.1-compatible JTAG boundary scan  
• 144-ball FBGA (13 mm × 13 mm) (1.0 mm pitch)  
• 120TQFP (14 mm x 14 mm x 1.4 mm)  
• Lead(Pb)-free packages available  
• Counter wrap around control  
— Internal mask register controls counter wrap-around  
— Counter-interrupt flags to indicate wrap-around  
— Memory block retransmit operation  
• Counter readback on address lines  
• Mask register readback on address lines  
The CY7C0833AV device in this family has limited features.  
Please see Address Counter and Mask Register  
Operations[15] on page 6 for details.  
• Dual Chip Enables on both ports for easy depth  
expansion  
Table 1. Product Selection Guide  
Density  
512-Kbit  
1-Mbit  
2-Mbit  
4-Mbit  
9-Mbit  
(32K x 18)  
(64K x 18)  
(128K x 18)  
(256K x 18)  
(512K x 18)  
Part Number  
CY7C0837AV CY7C0830AV CY7C0831AV CY7C0832AV CY7C0833AV  
Max. Speed (MHz)  
167  
4.0  
225  
167  
4.0  
225  
167  
4.0  
225  
167  
4.0  
225  
133  
4.7  
270  
Max. Access Time - clock to Data (ns)  
Typical operating current (mA)  
Package  
144 FBGA  
120 TQFP  
120 TQFP  
120 TQFP  
144 FBGA  
144 FBGA  
144 FBGA  
144 FBGA  
Cypress Semiconductor Corporation  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Document #: 38-06059 Rev. *Q  
Revised May 10, 2006  
[+] Feedback  
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与CY7C0837AV-133BBC相关器件

型号 品牌 获取价格 描述 数据表
CY7C0837AV-133BBI CYPRESS

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 		FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0837AV-167BBC CYPRESS

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 		FLEx18⑩ 3.3V 64K/128K x 36 and 128K/256K x 18
CY7C0837AV-167BBC ROCHESTER

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 		32KX18 DUAL-PORT SRAM, 4ns, PBGA144, 13 X 13 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-144
CY7C0837V CYPRESS

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 		FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
CY7C0837V-133BBC CYPRESS

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 		FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
CY7C0837V-133BBI CYPRESS

获取价格

 		FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
CY7C0837V-167BBC CYPRESS

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 		FLEx18-TM 3.3V 32K/64K/128K/256K/512K x 18 Synchronous Dual-Port RAM
CY7C0850AV CYPRESS

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 		FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850AV-133AC CYPRESS

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 		FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM
CY7C0850AV-133AI CYPRESS

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 		FLEx36TM 3.3V 32K/64K/128K/256K x 36 Synchronous Dual-Port RAM

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