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CY7C0851AV-133AXI PDF预览

CY7C0851AV-133AXI

更新时间： 2024-09-18 12:43:55
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
39页 661K
描述
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM

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CY7C0851AV-133AXI 技术参数

是否Rohs认证： 符合生命周期：Obsolete
零件包装代码：QFP包装说明：24 X 24 MM, 1.40 MM HEIGHT, ROHS COMPLIANT, TQFP-176
针数：176Reach Compliance Code：unknown
ECCN代码：3A991.B.2.AHTS代码：8542.32.00.41
Factory Lead Time：1 week风险等级：5.72
最长访问时间：4 ns其他特性：PIPELINED ARCHITECTURE
最大时钟频率 (fCLK)：133 MHzI/O 类型：COMMON
JESD-30 代码：S-PQFP-G176JESD-609代码：e3
长度：24 mm内存密度：2359296 bit
内存集成电路类型：DUAL-PORT SRAM内存宽度：36
湿度敏感等级：3功能数量：1
端口数量：2端子数量：176
字数：65536 words字数代码：64000
工作模式：SYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：64KX36
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：LFQFP封装等效代码：QFP176,1.0SQ,20
封装形状：SQUARE封装形式：FLATPACK, LOW PROFILE, FINE PITCH
并行/串行：PARALLEL峰值回流温度（摄氏度）：260
电源：3.3 V认证状态：Not Qualified
座面最大高度：1.6 mm最大待机电流：0.075 A
最小待机电流：3.14 V子类别：SRAMs
最大压摆率：0.3 mA最大供电电压 (Vsup)：3.465 V
最小供电电压 (Vsup)：3.135 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：CMOS
温度等级：INDUSTRIAL端子面层：Matte Tin (Sn)
端子形式：GULL WING端子节距：0.5 mm
端子位置：QUAD处于峰值回流温度下的最长时间：NOT SPECIFIED
宽度：24 mmBase Number Matches：1

CY7C0851AV-133AXI 数据手册

 浏览型号CY7C0851AV-133AXI的Datasheet PDF文件第2页浏览型号CY7C0851AV-133AXI的Datasheet PDF文件第3页浏览型号CY7C0851AV-133AXI的Datasheet PDF文件第4页浏览型号CY7C0851AV-133AXI的Datasheet PDF文件第5页浏览型号CY7C0851AV-133AXI的Datasheet PDF文件第6页浏览型号CY7C0851AV-133AXI的Datasheet PDF文件第7页 
CY7C0851V/CY7C0851AV  
CY7C0852V/CY7C0852AV  
CY7C0853V/CY7C0853AV  
FLEx36™ 3.3 V 32 K / 64 K / 128 K / 256 K × 36  
Synchronous Dual-Port RAM  
FLEx36™ 3.3  
V 32 K / 64 K / 128 K / 256 K × 36 Synchronous Dual-Port RAM  
Features  
Functional Description  
■ True dual-ported memory cells that allow simultaneous access  
of the same memory location  
The FLEx36™ family includes 2M, 4M, and 9M pipelined,  
synchronous, true dual-port static RAMs that are high-speed,  
low-power 3.3 V CMOS. Two ports are provided, permitting  
independent, simultaneous access to any location in memory.  
The result of writing to the same location by more than one port  
at the same time is undefined. Registers on control, address, and  
data lines allow for minimal setup and hold time.  
■ Synchronous pipelined operation  
■ Organization of 2-Mbit, 4-Mbit, and 9-Mbit devices  
■ Pipelined output mode allows fast operation  
■ 0.18-micron Complimentary metal oxide semiconductor  
(CMOS) for optimum speed and power  
During a Read operation, data is registered for decreased cycle  
time. Each port contains a burst counter on the input address  
register. After externally loading the counter with the initial  
address, the counter increments the address internally (more  
details to follow). The internal Write pulse width is independent  
of the duration of the R/W input signal. The internal Write pulse  
is self-timed to allow the shortest possible cycle times.  
■ High-speed clock to data access  
■ 3.3 V low power  
❐ Active as low as 225 mA (typ)  
❐ Standby as low as 55 mA (typ)  
A HIGH on CE0 or LOW on CE1 for one clock cycle powers down  
the internal circuitry to reduce the static power consumption. One  
cycle with chip enables asserted is required to reactivate the  
outputs.  
■ Mailbox function for message passing  
■ Global master reset  
■ Separate byte enables on both ports  
■ Commercial and industrial temperature ranges  
Additional features include: readback of burst-counter internal  
address value on address lines, counter-mask registers to  
control the counter wrap-around, counter interrupt (CNTINT)  
flags, readback of mask register value on address lines,  
retransmit functionality, interrupt flags for message passing,  
JTAG for boundary scan, and asynchronous Master Reset  
(MRST).  
■ IEEE 1149.1-compatible Joint test action group (JTAG)  
boundary scan  
■ 172-Ball fine-pitch ball grid array (FBGA) (1 mm pitch)  
(15 mm × 15 mm)  
The CY7C0853V/CY7C0853AV device in this family has limited  
features. Please see Address Counter and Mask Register  
Operations on page 9 for details.  
■ 176-Pin thin quad plastic flatpack (TQFP)  
(24 mm × 24 mm × 1.4 mm)  
■ Counter wrap around control  
❐ Internal mask register controls counter wrap-around  
❐ Counter-interrupt flags to indicate wrap-around  
❐ Memory block retransmit operation  
■ Counter readback on address lines  
■ Mask register readback on address lines  
■ Dual chip enables on both ports for easy depth expansion  
Product Selection Guide  
Density  
2-Mbit (64 K × 36)  
4-Mbit (128 K × 36)  
9-Mbit (256 K × 36)  
Part number  
CY7C0851V/CY7C0851AV  
CY7C0852V/CY7C0852AV  
CY7C0853V/CY7C0853AV  
Max. speed (MHz)  
167  
4.0  
167  
4.0  
133  
4.7  
Max. access time - clock to data (ns)  
Typical operating current (mA)  
Package  
225  
225  
270  
176-pin TQFP, 172-ball FBGA 176-pin TQFP, 172-ball FBGA  
172-ball FBGA  
Cypress Semiconductor Corporation  
Document Number: 38-06070 Rev. *L  
•
198 Champion Court  
•
San Jose, CA 95134-1709  
•
408-943-2600  
Revised August 7, 2012  
1234567...39

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