CY7C008-12AC

更新时间： 2024-09-16 22:06:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
19页	386K
描述
64K/128K x 8/9 Dual-Port Static RAM

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中文翻译

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数据手册

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CY7C008-12AC 数据手册

CY7C008/009

CY7C018/01964K/128K

x 8/9 Dual-Port Static RAM

CY7C008/009

CY7C018/019

64K/128K x 8/9 Dual-Port Static RAM

Features

• True Dual-Ported memory cells which allow simulta-

neous access of the same memory location

• Fully asynchronous operation

• Automatic power-down

• 64K x 8 organization (CY7C008)

• 128K x 8 organization (CY7C009)

• 64K x 9 organization (CY7C018)

• 128K x 9 organization (CY7C019)

• 0.35-micron CMOS for optimum speed/power

• High-speed access: 12^[1]/15/20 ns

• Low operating power

• Expandable data bus to 16/18 bits or more using Mas-

ter/Slave chip select when using more than one device

• On-chip arbitration logic

• Semaphores included to permit software handshaking

between ports

• INT flags for port-to-port communication

• Dual Chip Enables

• Pin select for Master or Slave

• Commercial and Industrial temperature ranges

• Available in 100-pin TQFP

— Active: I_CC= 180 mA (typical)

—Standby: I_SB3= 0.05 mA (typical)

Logic Block Diagram

R/W

[2]

8/9

I/O –I/O

7/8R

7/8L

I/O

Control

I/O

Control

16/17

[3]

A –A^[3]

–A

Address

Decode

Address

Decode

True Dual-Ported

15/16L

0R 15/16R

RAM Array

16/17

A –A^[3]

–A

[3]

15/16L

0R 15/16R

Interrupt

Semaphore

Arbitration

R/W

SEM

[4]

BUSY

INT

M/S

Notes:

1. See page 6 for Load Conditions.

2. I/O –I/O for x8 devices; I/O –I/O for x9 devices.

3. A –A for 64K devices; A –A for 128K.

4. BUSY is an output in master mode and an input in slave mode.

Cypress Semiconductor Corporation

Document #: 38-06041 Rev. *C

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Revised June 22, 2004

12 3 4 5 6 7...19

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