Datasheet > CY74FCT825TSOIC

CY74FCT825TSOIC

更新时间： 2024-11-25 09:43:03

品牌	Logo	应用领域
德州仪器 - TI		/
页数	文件大小	规格书
10页	88K
描述
8-/9-/10-Bit Bus Interface Registers

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CY74FCT825TSOIC 数据手册

Data sheet acquired from Cypress Semiconductor Corporation.

Data sheet modiﬁed to remove devices not offered.

CY74FCT821T

CY74FCT823T

CY74FCT825T

SCCS033 - May 1994 - Revised March 2000

8-/9-/10-Bit Bus Interface Registers

Features

Functional Description

• Function, pinout, and drive compatible with FCT, F, and

Am29821/23/25 logic

• FCT-C speed at 6.0 ns max.

FCT-B speed at 7.5 ns max.

• Reduced V_OH(typically = 3.3V) versions of equivalent

FCT functions

• Edge-rate control circuitry for signiﬁcantly improved

noise characteristics

These bus interface registers are designed to eliminate the

extra packages required to buffer existing registers and

provide extra data width for wider address/data paths or buses

carrying parity. The FCT821T is a buffered, 10-bit wide version

of the popular FCT374 function. The FCT823T is a 9-bit wide

buffered register with clock enable (EN) and clear (CLR) ideal

for parity bus interfacing in high-performance micropro-

grammed systems. The FCT825T is an 8-bit buffered register

with all the FCT823T controls plus multiple enables (OE₁,

OE₂, OE₃) to allow multiuser control of the interface, e.g., CS,

DMA, and RD/WR. They are ideal for use as an output port

• Power-off disable feature

• Matched rise and fall times

• Fully compatible with TTL input and output logic levels

• ESD > 2000V

requiring high I_OL/I_OH

These devices are designed for high-capacitance load drive

capability, while providing low-capacitance bus loading at both

inputs and outputs. Outputs are designed for low-capacitance

bus loading in the high-impedance state and are designed with

a power-off disable feature to allow for live insertion of boards.

• Sink current

Source current

64 mA

32 mA

• High-speed parallel registers with positive

edge-triggered D-type ﬂip-ﬂops

• Bufferedcommonclockenable(EN)andasynchronous

clear input (CLR)

• Extended commercial range of −40˚C to +85˚C

Logic Block Diagram

N- 1

[1]

CLR

Note:

1. Not on FCT821.

12 3 4 5 6 7...10

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与CY74FCT825TSOIC相关器件

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CY74FCT827ATQCT	TI	获取价格	10-Bit Buffer
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CY74FCT827ATQCTG4	TI	获取价格	10-BIT BUFFERS WITH 3-STATE OUTPUTS
CY74FCT827ATSOC	TI	获取价格	10-Bit Buffer
CY74FCT827ATSOCE4	TI	获取价格	10-BIT BUFFERS WITH 3-STATE OUTPUTS
CY74FCT827ATSOCG4	TI	获取价格	10-BIT BUFFERS WITH 3-STATE OUTPUTS
CY74FCT827ATSOCT	TI	获取价格	10-Bit Buffer
CY74FCT827ATSOCTE4	TI	获取价格	10-BIT BUFFERS WITH 3-STATE OUTPUTS
CY74FCT827ATSOCTG4	TI	获取价格	10-BIT BUFFERS WITH 3-STATE OUTPUTS
CY74FCT827BTSOCR	CYPRESS	获取价格	Bus Driver, FCT Series, 1-Func, 10-Bit, True Output, CMOS, PDSO24, 0.300 INCH, PLASTIC, SO

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