Data sheet acquired from Cypress Semiconductor Corporation.
Data sheet modified to remove devices not offered.
CY54/74FCT827T
SCCS034 - September 1994 - Revised March 2000
10-Bit Buffer
•
Sink current
64 mA (Com’l),
Features
32 mA (Mil)
Source current
32 mA (Com’l),
12 mA (Mil)
• Function, pinout, and drive compatible with FCT, F, and
AM29827 logic
• FCT-C speed at 4.4 ns max. (Com’l)
FCT-A speed at 5.0 ns max. (Com’l)
Functional Description
• Reduced VOH (typically = 3.3V) versions of equivalent
FCT functions
• Edge-rate control circuitry for significantly improved
noise characteristics
• Power-off disable feature
• ESD > 2000V
The FCT827T 10-bit bus driver provides high-performance
bus interface buffering for wide data/address paths or buses
carrying parity. The 10-bit buffers have NAND-ed output
enables for maximum control flexibility. The FCT827T is
designed for high-capacitance load drive capability, while providing
low-capacitance bus loading at both inputs and outputs. All outputs
are designed for low-capacitance bus loading in the
high-impedance state and are designed with a power-off disable
feature to allow for live insertion of boards.
• Matched rise and fall times
• Fully compatible with TTL input and output logic levels
Logic Block Diagram
Pin Configurations
LCC/PLCC
Top View
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
1110 9
12
8 7 6 5
D
D
GND
NC
4
D
D
8
1
13
14
3
2
1
9
0
OE
1
15
16
17
NC
V
OE
2
28
27
26
CC
Y
9
Y
0
Y
8
18
Y
1
1920 2122 23 24 25
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
OE OE
1
2
SOIC/QSOP
Top View
1
OE
1
24
V
CC
2
3
4
5
6
D
D
23
22
21
Y
0
0
1
Y
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
Y
2
Y
3
20
19
18
17
16
Y
4
Y
5
7
Y
6
8
Y
7
9
Y
8
10
11
12
15
14
13
Y
9
GND
OE
2
Function Table[1]
Inputs
OE2
Outputs
Y
OE1
D
Function
L
L
L
L
L
H
L
H
Transparent
H
X
X
H
X
X
Z
Z
Three-State
Note:
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care
Copyright © 2000, Texas Instruments Incorporated