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CY74FCT827CTQCT PDF预览

CY74FCT827CTQCT

更新时间: 2024-11-05 05:18:59
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 69K
描述
10-Bit Buffer

CY74FCT827CTQCT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SOIC
包装说明:GREEN, QSOP-24针数:24
Reach Compliance Code:compliantECCN代码:EAR99
HTS代码:8542.39.00.01Factory Lead Time:1 week
风险等级:0.87Is Samacsys:N
其他特性:WITH DUAL OUTPUT ENABLE控制类型:ENABLE LOW
计数方向:UNIDIRECTIONAL系列:FCT
JESD-30 代码:R-PDSO-G24JESD-609代码:e4
长度:8.65 mm负载电容(CL):50 pF
逻辑集成电路类型:BUS DRIVER最大I(ol):0.064 A
湿度敏感等级:2位数:10
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.24
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TR峰值回流温度(摄氏度):260
电源:5 V最大电源电流(ICC):0.2 mA
Prop。Delay @ Nom-Sup:4.4 ns传播延迟(tpd):10 ns
认证状态:Not Qualified座面最大高度:1.75 mm
子类别:Bus Driver/Transceivers最大供电电压 (Vsup):5.25 V
最小供电电压 (Vsup):4.75 V标称供电电压 (Vsup):5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:0.64 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A宽度:3.9 mm
Base Number Matches:1

CY74FCT827CTQCT 数据手册

 浏览型号CY74FCT827CTQCT的Datasheet PDF文件第2页浏览型号CY74FCT827CTQCT的Datasheet PDF文件第3页浏览型号CY74FCT827CTQCT的Datasheet PDF文件第4页浏览型号CY74FCT827CTQCT的Datasheet PDF文件第5页浏览型号CY74FCT827CTQCT的Datasheet PDF文件第6页浏览型号CY74FCT827CTQCT的Datasheet PDF文件第7页 
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY54/74FCT827T  
SCCS034 - September 1994 - Revised March 2000  
10-Bit Buffer  
Sink current  
64 mA (Com’l),  
Features  
32 mA (Mil)  
Source current  
32 mA (Com’l),  
12 mA (Mil)  
Function, pinout, and drive compatible with FCT, F, and  
AM29827 logic  
• FCT-C speed at 4.4 ns max. (Com’l)  
FCT-A speed at 5.0 ns max. (Com’l)  
Functional Description  
• Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
• Edge-rate control circuitry for significantly improved  
noise characteristics  
• Power-off disable feature  
ESD > 2000V  
The FCT827T 10-bit bus driver provides high-performance  
bus interface buffering for wide data/address paths or buses  
carrying parity. The 10-bit buffers have NAND-ed output  
enables for maximum control flexibility. The FCT827T is  
designed for high-capacitance load drive capability, while providing  
low-capacitance bus loading at both inputs and outputs. All outputs  
are designed for low-capacitance bus loading in the  
high-impedance state and are designed with a power-off disable  
feature to allow for live insertion of boards.  
• Matched rise and fall times  
• Fully compatible with TTL input and output logic levels  
Logic Block Diagram  
Pin Configurations  
LCC/PLCC  
Top View  
Y
0
Y
1
Y
2
Y
3
Y
4
Y
5
Y
6
Y
7
Y
8
Y
9
1110 9  
12  
8 7 6 5  
D
D
GND  
NC  
4
D
D
8
1
13  
14  
3
2
1
9
0
OE  
1
15  
16  
17  
NC  
V
OE  
2
28  
27  
26  
CC  
Y
9
Y
0
Y
8
18  
Y
1
1920 2122 23 24 25  
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
OE OE  
1
2
SOIC/QSOP  
Top View  
1
OE  
1
24  
V
CC  
2
3
4
5
6
D
D
23  
22  
21  
Y
0
0
1
Y
1
D
2
D
3
D
4
D
5
D
6
D
7
D
8
D
9
Y
2
Y
3
20  
19  
18  
17  
16  
Y
4
Y
5
7
Y
6
8
Y
7
9
Y
8
10  
11  
12  
15  
14  
13  
Y
9
GND  
OE  
2
Function Table[1]  
Inputs  
OE2  
Outputs  
Y
OE1  
D
Function  
L
L
L
L
L
H
L
H
Transparent  
H
X
X
H
X
X
Z
Z
Three-State  
Note:  
1. H = HIGH Voltage Level. L = LOW Voltage Level. X = Don’t Care  
Copyright © 2000, Texas Instruments Incorporated  

CY74FCT827CTQCT 替代型号

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