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CY74FCT2652ATQCTE4

更新时间： 2024-11-21 14:50:51
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德州仪器 - TI /
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CY74FCT2652ATQCTE4 数据手册

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CY74FCT2652T  
8-BIT REGISTERED TRANSCEIVER  
WITH 3-STATE OUTPUTS  
SCCS044B – MAY 1994 – REVISED NOVEMBER 2001  
Q PACKAGE  
(TOP VIEW)  
Function and Pinout Compatible With FCT  
and F Logic  
25-Ω Output Series Resistors Reduce  
Transmission-Line Reflection Noise  
CPAB  
SAB  
GAB  
V
CC  
CPBA  
SBA  
GBA  
1
24  
23  
22  
21  
20  
19  
18  
17  
16  
15  
14  
13  
2
Reduced V  
of Equivalent FCT Functions  
(Typically = 3.3 V) Versions  
3
OH  
A
4
1
A
2
B
5
Edge-Rate Control Circuitry for  
Significantly Improved Noise  
Characteristics  
1
A
B
2
6
3
A
4
7
B
3
A
B
4
8
5
I
Supports Partial-Power-Down Mode  
off  
A
6
B
9
5
Operation  
A
10  
11  
B
B
B
7
6
7
8
Matched Rise and Fall Times  
A
8
Fully Compatible With TTL Input and  
Output Logic Levels  
GND 12  
ESD Protection Exceeds JESD 22  
– 2000-V Human-Body Model (A114-A)  
– 200-V Machine Model (A115-A)  
– 1000-V Charged-Device Model (C101)  
12-mA Output Sink Current  
15-mA Output Source Current  
Independent Register for A and B Buses  
Multiplexed Real-Time and Stored Data  
Transfer  
3-State Outputs  
description  
The CY74FCT2652T consists of bus transceiver circuits, D-type flip-flops, and control circuitry arranged for  
multiplexed transmission of data directly from the input bus or from the internal storage registers. Control (GAB  
and GBA) inputs control the transceiver functions. Select-control (SAB and SBA) inputs select either real-time  
or stored data transfer.  
The circuitry used for select control eliminates the typical decoding glitch that occurs in a multiplexer during  
transition between stored and real-time data. A low input level selects real-time data, and a high level selects  
stored data. Data on the A or B data bus, or both, can be stored in the internal D flip-flops by low-to-high  
transitions at the appropriate clock (CPAB or CPBA) inputs, regardless of levels at the select- or enable-control  
inputs. When SAB and SBA are in the real-time transfer mode, it also is possible to store data without using  
the internal D-type flip-flops by simultaneously enabling GAB and GBA. In this configuration, each output  
reinforces its input. Thus, when all other data sources to the two sets of bus lines are at high impedance, each  
set of bus lines remains at its last state.  
On-chip termination resistors at the outputs reduce system noise caused by reflections. The CY74FCT2652T  
can replace the CY74FCT652T to reduce noise in existing designs.  
This device is fully specified for partial-power-down applications using I . The I circuitry disables the outputs,  
off  
off  
preventing damaging current backflow through the device when it is powered down.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Copyright 2001, Texas Instruments Incorporated  
PRODUCTION DATA information is current as of publication date.  
Products conform to specifications per the terms of Texas Instruments  
standard warranty. Production processing does not necessarily include  
testing of all parameters.  
1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...15

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CY74FCT2652ATQCTE4 替代型号

型号 品牌 替代类型 描述 数据表
CY74FCT2652ATQCTG4 TI

类似代替

 FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, GREEN, PLASTIC, QSOP-24
CY74FCT2652ATQCT TI

类似代替

 8-Bit Registered Transceiver
CY74FCT2652ATQC TI

功能相似

 FCT SERIES, 8-BIT REGISTERED TRANSCEIVER, TRUE OUTPUT, PDSO24, 0.150 INCH, QSOP-24

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