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CY74FCT2652TSOIC

更新时间： 2024-11-21 09:42:59
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德州仪器 - TI /
页数 文件大小 规格书
7页 54K
描述
8-Bit Registered Transceiver

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CY74FCT2652TSOIC 数据手册

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1CY54/  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT2652T  
SCCS044 - May 1994 - Revised March 2000  
8-Bit Registered Transceiver  
mission of data directly from the input bus or from the internal  
storage registers. GAB and GBA control pins are provided to  
control the transceiver functions. SAB and SBA control pins are  
provided to select either real-time or stored data transfer.  
Features  
•
Function and pinout compatible with FCT and F logic  
•
FCT-C speed at 5.4 ns max. (Com’l)  
FCT-A speed at 6.3 ns max. (Com’l)  
The circuitry used for select control will eliminate the typical  
decoding glitch that occurs in a multiplexer during transition  
between stored and real-time data. A LOW input level selects  
real-time data and a HIGH selects stored data. Data on the A  
or B data bus, or both, can be stored in the internal D flip-flops  
by LOW-to-HIGH transitions at the appropriate clock pins  
(CPAB or CPBA), regardless of the select or enable control  
pins. When SAB and SBA are in the real-time transfer mode,  
it is also possible to store data without using the internal  
D-type flip-flops by simultaneously enabling GAB and GBA. In  
this configuration, each output reinforces its input. Thus, when all  
other data sources to the two sets of bus lines are at high imped-  
ance, each set of bus lines will remain at its last state.  
•
•
•
25Ω output series resistors to reduce transmission line  
reflection noise  
Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
Edge-rate control circuitry for significantly improved  
noise characteristics  
•
•
•
•
Power-off disable feature  
Matched rise and fall times  
Fully compatible with TTL input and output logic levels  
Sink current  
Source current  
12 mA  
15 mA  
•
•
•
•
ESD > 2000V  
On-chip termination resistors are added to the outputs to  
reduce system noise caused by reflections. The FCT2652T  
can replace the FCT652T to reduce noise in existing designs.  
Independent register for A and B buses  
Multiplexed real-time and stored data transfer  
Extended commercial temp. range of –40˚C to +85˚C  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards  
Functional Description  
The FCT2652T consists of bus transceiver circuits, D-type  
flip-flops, and control circuitry arranged for multiplexed trans-  
LogicBlockDiagram  
Pin Configurations  
CPBA  
GAB  
SBA  
SAB  
SOIC/QSOP  
Top View  
GBA  
CPAB  
1
CPAB  
SAB  
24  
23  
22  
21  
BREG  
V
CC  
CPBA  
2
1OF8CHANNELS  
3
GAB  
SBA  
D
4
A
1
GBA  
C
A
2
5
B
1
20  
19  
A
3
B
2
6
A
1
A
4
B
3
7
18  
17  
16  
A
5
B
4
8
AREG  
D
B
1
A
6
B
5
9
A
7
B
6
10  
11  
12  
15  
14  
13  
A
8
B
7
C
GND  
B
8
FCT2652T–3  
TO  
7 OTHERCHANNELS  
FCT2652T–1  
Copyright © 2000, Texas Instruments Incorporated  
1234567

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