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CY74FCT2652CTQCT PDF预览

CY74FCT2652CTQCT

更新时间: 2024-11-25 09:42:59
品牌 Logo 应用领域
德州仪器 - TI 总线驱动器总线收发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
7页 54K
描述
8-Bit Registered Transceiver

CY74FCT2652CTQCT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:SOIC
包装说明:SSOP, SSOP24,.24针数:24
Reach Compliance Code:compliantHTS代码:8542.39.00.01
风险等级:5.66Is Samacsys:N
控制类型:INDEPENDENT CONTROL计数方向:BIDIRECTIONAL
系列:FCTJESD-30 代码:R-PDSO-G24
长度:8.65 mm逻辑集成电路类型:REGISTERED BUS TRANSCEIVER
最大I(ol):0.012 A位数:8
功能数量:1端口数量:2
端子数量:24最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE WITH SERIES RESISTOR
输出极性:TRUE封装主体材料:PLASTIC/EPOXY
封装代码:SSOP封装等效代码:SSOP24,.24
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
包装方法:TAPE AND REEL峰值回流温度(摄氏度):NOT SPECIFIED
电源:5 VProp。Delay @ Nom-Sup:5.4 ns
传播延迟(tpd):5.4 ns认证状态:Not Qualified
座面最大高度:1.75 mm子类别:Bus Driver/Transceivers
最大供电电压 (Vsup):5.25 V最小供电电压 (Vsup):4.75 V
标称供电电压 (Vsup):5 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子形式:GULL WING端子节距:0.635 mm
端子位置:DUAL处于峰值回流温度下的最长时间:NOT SPECIFIED
翻译:N/A触发器类型:POSITIVE EDGE
宽度:3.9 mmBase Number Matches:1

CY74FCT2652CTQCT 数据手册

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1CY54/  
Data sheet acquired from Cypress Semiconductor Corporation.  
Data sheet modified to remove devices not offered.  
CY74FCT2652T  
SCCS044 - May 1994 - Revised March 2000  
8-Bit Registered Transceiver  
mission of data directly from the input bus or from the internal  
storage registers. GAB and GBA control pins are provided to  
control the transceiver functions. SAB and SBA control pins are  
provided to select either real-time or stored data transfer.  
Features  
Function and pinout compatible with FCT and F logic  
FCT-C speed at 5.4 ns max. (Com’l)  
FCT-A speed at 6.3 ns max. (Com’l)  
The circuitry used for select control will eliminate the typical  
decoding glitch that occurs in a multiplexer during transition  
between stored and real-time data. A LOW input level selects  
real-time data and a HIGH selects stored data. Data on the A  
or B data bus, or both, can be stored in the internal D flip-flops  
by LOW-to-HIGH transitions at the appropriate clock pins  
(CPAB or CPBA), regardless of the select or enable control  
pins. When SAB and SBA are in the real-time transfer mode,  
it is also possible to store data without using the internal  
D-type flip-flops by simultaneously enabling GAB and GBA. In  
this configuration, each output reinforces its input. Thus, when all  
other data sources to the two sets of bus lines are at high imped-  
ance, each set of bus lines will remain at its last state.  
25output series resistors to reduce transmission line  
reflection noise  
Reduced VOH (typically = 3.3V) versions of equivalent  
FCT functions  
Edge-rate control circuitry for significantly improved  
noise characteristics  
Power-off disable feature  
Matched rise and fall times  
Fully compatible with TTL input and output logic levels  
Sink current  
Source current  
12 mA  
15 mA  
ESD > 2000V  
On-chip termination resistors are added to the outputs to  
reduce system noise caused by reflections. The FCT2652T  
can replace the FCT652T to reduce noise in existing designs.  
Independent register for A and B buses  
Multiplexed real-time and stored data transfer  
Extended commercial temp. range of –40˚C to +85˚C  
The outputs are designed with a power-off disable feature to  
allow for live insertion of boards  
Functional Description  
The FCT2652T consists of bus transceiver circuits, D-type  
flip-flops, and control circuitry arranged for multiplexed trans-  
LogicBlockDiagram  
Pin Configurations  
CPBA  
GAB  
SBA  
SAB  
SOIC/QSOP  
Top View  
GBA  
CPAB  
1
CPAB  
SAB  
24  
23  
22  
21  
BREG  
V
CC  
CPBA  
2
1OF8CHANNELS  
3
GAB  
SBA  
D
4
A
1
GBA  
C
A
2
5
B
1
20  
19  
A
3
B
2
6
A
1
A
4
B
3
7
18  
17  
16  
A
5
B
4
8
AREG  
D
B
1
A
6
B
5
9
A
7
B
6
10  
11  
12  
15  
14  
13  
A
8
B
7
C
GND  
B
8
FCT2652T–3  
TO  
7 OTHERCHANNELS  
FCT2652T1  
Copyright © 2000, Texas Instruments Incorporated  

CY74FCT2652CTQCT 替代型号

型号 品牌 替代类型 描述 数据表
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