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CY62256LL-70ZXIT PDF预览

CY62256LL-70ZXIT

更新时间: 2024-02-27 18:15:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器光电二极管
页数 文件大小 规格书
14页 476K
描述
暂无描述

CY62256LL-70ZXIT 数据手册

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CY62256  
256K (32K x 8) Static RAM  
Features  
Functional Description[1]  
• High speed  
The CY62256 is a high-performance CMOS static RAM  
organized as 32K words by 8 bits. Easy memory expansion is  
provided by an active LOW chip enable (CE) and active LOW  
output enable (OE) and Tri-state drivers. This device has an  
automatic power-down feature, reducing the power  
consumption by 99.9% when deselected.  
— 55 ns  
• Temperature Ranges  
— Commercial: 0°C to 70°C  
— Industrial: –40°C to 85°C  
— Automotive: –40°C to 125°C  
• Voltage range  
An active LOW write enable signal (WE) controls the  
writing/reading operation of the memory. When CE and WE  
inputs are both LOW, data on the eight data input/output pins  
(I/O0 through I/O7) is written into the memory location  
addressed by the address present on the address pins (A0  
through A14). Reading the device is accomplished by selecting  
the device and enabling the outputs, CE and OE active LOW,  
while WE remains inactive or HIGH. Under these conditions,  
the contents of the location addressed by the information on  
address pins are present on the eight data input/output pins.  
— 4.5V – 5.5V  
• Low active power and standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
The input/output pins remain in a high-impedance state unless  
the chip is selected, outputs are enabled, and write enable  
(WE) is HIGH.  
• Available in a Pb-free and non Pb-free standard 28-pin  
narrow SOIC, 28-pin TSOP-1, 28-pin Reverse TSOP-1  
and 28-pin DIP packages  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
INPUTBUFFER  
A
A
A
10  
9
8
A
7
6
5
32K × 8  
ARRAY  
A
A
A
A
A
4
3
2
CE  
WE  
POWER  
DOWN  
COLUMN  
DECODER  
I/O  
7
OE  
Note:  
1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05248 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 3, 2006  
[+] Feedback  

CY62256LL-70ZXIT 替代型号

型号 品牌 替代类型 描述 数据表
CY62256NLL-55ZXIT CYPRESS

功能相似

Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28

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