Datasheet > CY62256N_09

CY62256N_09

更新时间： 2024-09-29 06:51:35

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
14页	567K
描述
256K (32K x 8) Static RAM

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中文翻译

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CY62256N_09 数据手册

CY62256N

256K (32K x 8) Static RAM

Features

Functional Description

■ Temperature Ranges

The CY62256N^[1]is a high performance CMOS static RAM

organized as 32K words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE) and active LOW

output enable (OE) and tristate drivers. This device has an

automatic power down feature, reducing the power consumption

by 99.9 percent when deselected.

❐ Commercial: 0°C to 70°C

❐ Industrial: –40°C to 85°C

❐ Automotive-A: –40°C to 85°C

❐ Automotive-E: –40°C to 125°C

■ High Speed: 55 ns

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O₀through I/O₇) is written into the memory location addressed

by the address present on the address pins (A₀through A₁₄).

Reading the device is accomplished by selecting the device and

enabling the outputs, CE and OE active LOW, while WE remains

inactive or HIGH. Under these conditions, the contents of the

location addressed by the information on address pins are

present on the eight data input/output pins.

■ Voltage Range: 4.5V to 5.5V Operation

■ Low Active Power

❐ 275 mW (max)

■ Low Standby Power (LL version)

❐ 82.5 μW (max)

■ Easy Memory Expansion with CE and OE Features

■ TTL-Compatible Inputs and Outputs

The input/output pins remain in a high impedance state unless

the chip is selected, outputs are enabled, and write enable (WE)

is HIGH.

■ Automatic Power Down when Deselected

■ CMOS for Optimum Speed and Power

■ Available in Pb-free and Non Pb-free 28-Pin (600-mil) PDIP,

28-Pin (300-mil) Narrow SOIC, 28-Pin TSOP-I, and 28-Pin

Reverse TSOP-I Packages

Logic Block Diagram

I/O

INPUTBUFFER

32K x 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note

1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com

Cypress Semiconductor Corporation

Document #: 001-06511 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 03, 2009

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中文翻译

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与CY62256N_09相关器件

型号	品牌	获取价格	描述	数据表
CY62256N_11	CYPRESS	获取价格	256K (32K × 8) Static RAM
CY62256NL-70PC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NL-70PC	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDIP28, 0.600 INCH, MS-011, DIP-28
CY62256NL-70PXC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NL-70SNC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NL-70SNC	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, SOIC-28
CY62256NL-70SNCT	CYPRESS	获取价格	暂无描述
CY62256NL-70SNI	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NL-70SNXC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NL-70SNXC	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, LEAD FREE, SOIC-28

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