Datasheet > 存储 > SRAM> CY62256NLL-55ZXI

CY62256NLL-55ZXI

更新时间： 2024-01-21 15:06:44

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
13页	710K
描述
256K (32K x 8) Static RAM

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数据手册
替代型号

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CY62256NLL-55ZXI 数据手册

CY62256N

256K (32K x 8) Static RAM

Features

Functional Description^[1]

• Temperature Ranges

The CY62256N is a high-performance CMOS static RAM

organized as 32K words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE) and active LOW

output enable (OE) and tri-state drivers. This device has an

automatic power-down feature, reducing the power

consumption by 99.9% when deselected.

— Commercial: 0°C to 70°C

— Industrial: –40°C to 85°C

— Automotive-A: –40°C to 85°C

— Automotive-E: –40°C to 125°C

• High speed: 55 ns

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O₀through I/O₇) is written into the memory location

addressed by the address present on the address pins (A₀

through A₁₄). Reading the device is accomplished by selecting

the device and enabling the outputs, CE and OE active LOW,

while WE remains inactive or HIGH. Under these conditions,

the contents of the location addressed by the information on

address pins are present on the eight data input/output pins.

• Voltage range: 4.5V–5.5V operation

• Low active power

— 275 mW (max.)

• Low standby power (LL version)

— 82.5 µW (max.)

• Easy memory expansion with CE and OE features

• TTL-compatible inputs and outputs

• Automatic power-down when deselected

• CMOS for optimum speed/power

The input/output pins remain in a high-impedance state unless

the chip is selected, outputs are enabled, and write enable

(WE) is HIGH.

• Available in pb-free and non Pb-free 28-lead (600-mil)

PDIP, 28-lead (300-mil) narrow SOIC, 28-lead TSOP-I

and 28-lead Reverse TSOP-I packages

Logic Block Diagram

I/O

INPUTBUFFER

32K x 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note:

1. For best practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 001-06511 Rev. *A

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 3, 2006

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CY62256NLL-55ZXI 替代型号

型号	品牌	替代类型	描述	数据表
CY62256NLL-55ZXA	CYPRESS	完全替代	256K (32K x 8) Static RAM
CY62256NLL-55ZXIT	CYPRESS	类似代替	Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28
CY62256LL-70ZC	CYPRESS	类似代替	256K (32K x 8) Static RAM

与CY62256NLL-55ZXI相关器件

型号	品牌	获取价格	描述	数据表
CY62256NLL-55ZXIT	CYPRESS	获取价格	Standard SRAM, 32KX8, 55ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28
CY62256NLL-70PC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NLL-70PXC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NLL-70SNC	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NLL-70SNC	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, SOIC-28
CY62256NLL-70SNCT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, SOIC-28
CY62256NLL-70SNI	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256NLL-70SNIT	CYPRESS	获取价格	Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, SOIC-28
CY62256NLL-70SNIT	ROCHESTER	获取价格	32KX8 STANDARD SRAM, 70ns, PDSO28, 0.300 INCH, SOIC-28
CY62256NLL-70SNXA	CYPRESS	获取价格	256K (32K x 8) Static RAM

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