Datasheet > CY62256NLL-70ZXIT

CY62256NLL-70ZXIT

更新时间： 2024-11-26 10:55:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器光电二极管
页数	文件大小	规格书
14页	574K
描述
Standard SRAM, 32KX8, 70ns, CMOS, PDSO28, 8 X 13.40 MM, LEAD FREE, TSOP1-28

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CY62256N

256K (32K x 8) Static RAM

Features

Functional Description

■ Temperature Ranges

The CY62256N^[1]is a high performance CMOS static RAM

organized as 32K words by 8 bits. Easy memory expansion is

provided by an active LOW chip enable (CE) and active LOW

output enable (OE) and tristate drivers. This device has an

automatic power down feature, reducing the power consumption

by 99.9 percent when deselected.

❐ Commercial: 0°C to 70°C

❐ Industrial: –40°C to 85°C

❐ Automotive-A: –40°C to 85°C

❐ Automotive-E: –40°C to 125°C

■ High Speed: 55 ns

An active LOW write enable signal (WE) controls the

writing/reading operation of the memory. When CE and WE

inputs are both LOW, data on the eight data input/output pins

(I/O₀through I/O₇) is written into the memory location addressed

by the address present on the address pins (A₀through A₁₄).

Reading the device is accomplished by selecting the device and

enabling the outputs, CE and OE active LOW, while WE remains

inactive or HIGH. Under these conditions, the contents of the

location addressed by the information on address pins are

present on the eight data input/output pins.

■ Voltage Range: 4.5V to 5.5V Operation

■ Low Active Power

❐ 275 mW (max)

■ Low Standby Power (LL version)

❐ 82.5 μW (max)

■ Easy Memory Expansion with CE and OE Features

■ TTL-Compatible Inputs and Outputs

The input/output pins remain in a high impedance state unless

the chip is selected, outputs are enabled, and write enable (WE)

is HIGH.

■ Automatic Power Down when Deselected

■ CMOS for Optimum Speed and Power

■ Available in Pb-free and Non Pb-free 28-Pin (600-mil) PDIP,

28-Pin (300-mil) Narrow SOIC, 28-Pin TSOP-I, and 28-Pin

Reverse TSOP-I Packages

Logic Block Diagram

I/O

INPUTBUFFER

32K x 8

ARRAY

POWER

DOWN

COLUMN

DECODER

I/O

Note

1. For best practice recommendations, do refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com

Cypress Semiconductor Corporation

Document #: 001-06511 Rev. *B

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 03, 2009

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与CY62256NLL-70ZXIT相关器件

型号	品牌	获取价格	描述	数据表
CY62256V	CYPRESS	获取价格	32K x 8 Static RAM
CY62256V_06	CYPRESS	获取价格	256K (32K x 8) Static RAM
CY62256V18L-200ZC	CYPRESS	获取价格	Standard SRAM, 32KX8, 200ns, CMOS, PDSO28, TSOP1-28
CY62256V18L-200ZRC	CYPRESS	获取价格	Standard SRAM, 32KX8, 200ns, CMOS, PDSO28, REVERSE, TSOP1-28
CY62256V25-70SNC	CYPRESS	获取价格	Cache SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, SOIC-28
CY62256V25-70ZC	CYPRESS	获取价格	Cache SRAM, 32KX8, 70ns, CMOS, PDSO28, TSOP1-28
CY62256V25L-70SNC	CYPRESS	获取价格	Cache SRAM, 32KX8, 70ns, CMOS, PDSO28, 0.300 INCH, SOIC-28
CY62256V25LL	CYPRESS	获取价格	32K x 8 Static RAM
CY62256V25LL-100ZC	CYPRESS	获取价格	32K x 8 Static RAM
CY62256V25LL-100ZCT	CYPRESS	获取价格	暂无描述

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