fax id: 1072
CY62128
128K x 8 Static RAM
feature that reduces power consumption by more than 75%
when deselected.
Features
• 4.5V 5.5V operation
−
Writing to the device is accomplished by taking chip enable
• CMOS for optimum speed/power
• Low active power (70 ns, LL version)
— 330 mW (max.) (60 mA)
one (CE ) and write enable (WE) inputs LOW and chip enable
1
two (CE ) input HIGH. Data on the eight I/O pins (I/O through
2
0
I/O ) is then written into the location specified on the address
7
pins (A through A ).
0
16
• Low standby power (70 ns, LL version)
Reading from the device is accomplished by taking chip en-
able one (CE ) and output enable (OE) LOW while forcing
— 110 W (max.) (20 A)
µ
µ
1
• Automatic power-down when deselected
• TTL-compatible inputs and outputs
• Easy memory expansion with CE , CE , and OE options
write enable (WE) and chip enable two (CE ) HIGH. Under
2
these conditions, the contents of the memory location speci-
fied by the address pins will appear on the I/O pins.
1
2
The eight input/output pins (I/O through I/O ) are placed in a
0
7
Functional Description
high-impedance state when the device is deselected (CE
1
HIGH or CE LOW), the outputs are disabled (OE HIGH), or
2
The CY62128 is a high-performance CMOS static RAM orga-
nized as 131,072 words by 8 bits. Easy memory expansion is
during a write operation (CE LOW, CE HIGH, and WE LOW).
1
2
The CY62128 is available in a standard 450-mil-wide SOIC,
32-pin TSOP type I and STSOP packages.
provided by an active LOW chip enable (CE ), an active HIGH
1
chip enable (CE ), an active LOW output enable (OE), and
2
three-state drivers. This device has an automatic power-down
Logic Block Diagram
Pin
Configurations
Top View
SOIC
V
NC
32
31
30
1
CC
A
A
A
16
14
12
A
2
3
4
15
CE
2
29
28
WE
A
I/O
0
5
A
A
7
13
INPUTBUFFER
27
26
6
A
8
A
9
6
A
5
7
I/O
1
A
0
25
24
23
22
21
A
A
3
8
9
10
11
12
13
4
A
11
A
1
OE
I/O
2
A
2
A
A
10
2
A
3
A
1
CE
1
A
4
I/O
3
512x256x8
ARRAY
I/O
7
A
0
0
A
5
I/O
I/O
I/O
I/O
6
20
19
A
6
I/O
4
I/O
1
2
5
4
3
A
14
15
16
7
A
I/O
I/O
8
18
17
I/O
5
GND
I/O
6
POWER
DOWN
COLUMN
DECODER
CE
1
2
CE
I/O
7
WE
62128-1
A
OE
A
A
A
A
A
A
1
2
4
5
16
15
14
13
12
11
10
9
8
7
6
5
4
3
32
OE
11
17
3
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
A
A
1
A
10
9
8
2
18
19
3
4
5
6
7
8
A
A
CE
6
7
1
A
I/O
I/O
I/O
GND
I/O
I/O
4
I/O
I/O
7
I/O
6
I/O
5
I/O
4
I/O
3
13
20
21
22
23
24
25
26
27
28
29
30
0
A
A
WE
CE
A
12
14
0
1
2
2
TSOP I
TSOP I/ STSOP
Top View
(not to scale)
A
15
16
V
NC
CC
Reverse Pinout
Top View
(not to scale)
CC
V
NC
A
A
A
A
7
A
6
9
GND
3
I/O
2
A
10
11
12
13
14
15
16
16
15
I/O
1
CE
WE
5
2
14
12
I/O
6
I/O
CE
1
I/O
0
A
0
A
7
13
A
A
A
9
1
8
A
10
A
2
A
3
A
5
A
4
31
32
2
1
A
OE
11
62128-2
62128-2
Cypress Semiconductor Corporation
•
3901 North First Street
•
San Jose
•
CA 95134
•
408-943-2600
July 1996 - Revised June 18, 1998