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CY62128DV30LL-55ZRI PDF预览

CY62128DV30LL-55ZRI

更新时间： 2024-09-29 22:06:31
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
11页 198K
描述
1 Mb (128K x 8) Static RAM

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中文翻译

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CY62128DV30LL-55ZRI 技术参数

是否Rohs认证： 不符合生命周期：Obsolete
零件包装代码：TSOP1包装说明：REVERSE, TSOP1-32
针数：32Reach Compliance Code：not_compliant
ECCN代码：EAR99HTS代码：8542.32.00.41
风险等级：5.52最长访问时间：55 ns
I/O 类型：COMMONJESD-30 代码：R-PDSO-G32
JESD-609代码：e0长度：18.4 mm
内存密度：1048576 bit内存集成电路类型：STANDARD SRAM
内存宽度：8湿度敏感等级：3
功能数量：1端子数量：32
字数：131072 words字数代码：128000
工作模式：ASYNCHRONOUS最高工作温度：85 °C
最低工作温度：-40 °C组织：128KX8
输出特性：3-STATE封装主体材料：PLASTIC/EPOXY
封装代码：TSOP1-R封装等效代码：TSSOP32,.8,20
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE
并行/串行：PARALLEL峰值回流温度（摄氏度）：240
电源：2.5/3.3 V认证状态：Not Qualified
反向引出线：YES座面最大高度：1.2 mm
最大待机电流：0.000003 A最小待机电流：1.5 V
子类别：SRAMs最大压摆率：0.01 mA
最大供电电压 (Vsup)：3.6 V最小供电电压 (Vsup)：2.2 V
标称供电电压 (Vsup)：3 V表面贴装：YES
技术：CMOS温度等级：INDUSTRIAL
端子面层：Tin/Lead (Sn/Pb)端子形式：GULL WING
端子节距：0.5 mm端子位置：DUAL
处于峰值回流温度下的最长时间：30宽度：8 mm
Base Number Matches：1

CY62128DV30LL-55ZRI 数据手册

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CY62128DV30  
MoBL  
1 Mb (128K x 8) Static RAM  
power consumption by 90% when addresses are not toggling.  
The device can be put into standby mode reducing power con-  
sumption by more than 99% when deselected Chip Enable 1  
(CE1) HIGH or Chip Enable 2 (CE2) LOW. The input/output  
pins (I/O0 through I/O7) are placed in a high-impedance state  
when: deselected Chip Enable 1 (CE1) HIGH or Chip Enable  
2 (CE2) LOW, outputs are disabled (OE HIGH), or during a  
write operation (Chip Enable 1 (CE1) LOW and Chip Enable 2  
(CE2) HIGH and Write Enable (WE) LOW).  
Features  
• Very high speed: 55 and 70 ns  
• Wide voltage range: 2.2V to 3.6V  
• Pin compatible with CY62128V  
• Ultra-low active power  
— Typical active current: 0.85 mA @ f = 1 MHz  
— Typical active current: 5 mA @ f = fMAX  
• Ultra-low standby power  
Writing to the device is accomplished by taking Chip Enable 1  
(CE1) LOW with Chip Enable 2 (CE2) HIGH and Write En-  
able(WE) LOW. Data on the eight I/O pins is then written into  
the location specified on the Address pin (A0 thro. A16).  
• Easy memory expansion with CE1, CE2, and OE  
features  
• Automatic power-down when deselected  
• Packages offered in a 32-lead SOIC, a 32-lead TSOP, a  
32-lead Short TSOP, and a 32-lead Reverse TSOP  
Reading from the device is accomplished by taking Chip En-  
able 1 (CE1) LOW with Chip Enable 2 (CE2) HIGH and Output  
Enable (OE) LOW while forcing the Write Enable (WE) HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the I/O pins.  
Functional Description[1]  
The CY62128DV30 is a high-performance CMOS static RAM  
organized as 128K words by 8 bits. This device features ad-  
vanced circuit design to provide ultra-low active current. This  
is ideal for providing More Battery Life(MoBL®) in portable  
applications such as cellular telephones. The device also has  
an automatic power-down feature that significantly reduces  
The eight input/output pins (I/Oo through I/O7) are placed in a  
high-impedance state when the device is deselected (CE1  
HIGH or CE2 LOW), the outputs are disabled (OE HIGH) or  
during a write operation (CE1 LOW, CE2 HIGH), and WE  
LOW).  
Logic Block Diagram  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
I/O  
0
1
2
3
4
5
6
Data in Drivers  
A
A
A
A
A
A
0
1
2
3
4
5
6
7
A
128K x 8  
ARRAY  
A
A
A
A10  
A11  
8
9
Power-  
down  
CE  
CE  
COLUMN  
DECODER  
1
2
I/O  
WE  
OE  
7
Note:  
1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.  
Cypress Semiconductor Corporation  
Document #: 38-05231 Rev. *C  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Revised August 29, 2003  
1234567...11

中文翻译

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CY62128DV30LL-55ZRIT CYPRESS

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 		Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, REVERSE, TSOP1-32
CY62128DV30LL-55ZRXI CYPRESS

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 		1-Mb (128K x 8) Static RAM
CY62128DV30LL-55ZRXIT CYPRESS

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CY62128DV30LL-55ZXI CYPRESS

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 		1-Mb (128K x 8) Static RAM
CY62128DV30LL-55ZXI ROCHESTER

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 		128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY62128DV30LL-55ZXIT CYPRESS

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 		Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY62128DV30LL-70SI CYPRESS

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 		1 Mb (128K x 8) Static RAM
CY62128DV30LL-70SXI CYPRESS

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 		1-Mb (128K x 8) Static RAM
CY62128DV30LL-70SXI ROCHESTER

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 		128KX8 STANDARD SRAM, 70ns, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62128DV30LL-70SXIT CYPRESS

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 		Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32

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