Datasheet > CY62128DV30LL-55ZRXIT

CY62128DV30LL-55ZRXIT

更新时间： 2024-10-01 08:18:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		静态存储器光电二极管
页数	文件大小	规格书
11页	578K
描述
Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, REVERSE, TSOP1-32

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CY62128DV30

1-Mb (128K x 8) Static RAM

also has an automatic power-down feature that significantly

reduces power consumption by 90% when addresses are not

toggling. The device can be put into standby mode reducing

power consumption by more than 99% when deselected Chip

Enable 1 (CE₁) HIGH or Chip Enable 2 (CE₂) LOW. The

input/output pins (I/O₀through I/O₇) are placed in a

high-impedance state when: deselected Chip Enable 1 (CE₁)

HIGH or Chip Enable 2 (CE₂) LOW, outputs are disabled (OE

HIGH), or during a write operation (Chip Enable 1 (CE₁) LOW

and Chip Enable 2 (CE₂) HIGH and Write Enable (WE) LOW).

Features

• Very high speed: 55 and 70 ns

• Wide voltage range: 2.2V to 3.6V

• Pin compatible with CY62128V

• Ultra-low active power

— Typical active current: 0.85 mA @ f = 1 MHz

— Typical active current: 5 mA @ f = f_MAX

• Ultra-low standby power

Writing to the device is accomplished by taking Chip Enable 1

(CE₁) LOW with Chip Enable 2 (CE₂) HIGH and Write Enable

(WE) LOW. Data on the eight I/O pins is then written into the

location specified on the Address pin (A₀through A₁₆).

• Easy memory expansion with CE₁, CE₂, and OE

features

• Automatic power-down when deselected

Reading from the device is accomplished by taking Chip

Enable 1 (CE₁) LOW with Chip Enable 2 (CE₂) HIGH and

Output Enable (OE) LOW while forcing the Write Enable (WE)

HIGH. Under these conditions, the contents of the memory

location specified by the address pins will appear on the I/O

pins.

• Available in Pb-free and non Pb-free 32-lead SOIC,

32-lead TSOP and 32-lead Small TSOP, non Pb-free

32-lead Reverse TSOP packages

Functional Description^[1]

The eight input/output pins (I/O_othrough I/O₇) are placed in a

high-impedance state when the device is deselected (CE₁

HIGH or CE₂LOW), the outputs are disabled (OE HIGH) or

during a write operation (CE₁LOW, CE₂HIGH), and WE

LOW).

The CY62128DV30 is a high-performance CMOS static RAM

organized as 128K words by 8 bits. This device features

advanced circuit design to provide ultra-low active current.

This is ideal for providing More Battery Life™ (MoBL^®) in

portable applications such as cellular telephones. The device

Logic Block Diagram

I/O

Data in Drivers

I/O

128K x 8

ARRAY

I/O

A10

A11

I/O

Power-

down

COLUMN

DECODER

I/O

Note:

1. For best-practice recommendations, please refer to the Cypress application note “System Design Guidelines” on http://www.cypress.com.

Cypress Semiconductor Corporation

Document #: 38-05231 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised June 19, 2006

12 3 4 5 6 7...11

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与CY62128DV30LL-55ZRXIT相关器件

型号	品牌	获取价格	描述	数据表
CY62128DV30LL-55ZXI	CYPRESS	获取价格	1-Mb (128K x 8) Static RAM
CY62128DV30LL-55ZXI	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 55ns, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY62128DV30LL-55ZXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 55ns, CMOS, PDSO32, 8 X 20 MM, LEAD FREE, TSOP1-32
CY62128DV30LL-70SI	CYPRESS	获取价格	1 Mb (128K x 8) Static RAM
CY62128DV30LL-70SXI	CYPRESS	获取价格	1-Mb (128K x 8) Static RAM
CY62128DV30LL-70SXI	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 70ns, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62128DV30LL-70SXIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 0.450 INCH, LEAD FREE, SOIC-32
CY62128DV30LL-70ZAI	CYPRESS	获取价格	1 Mb (128K x 8) Static RAM
CY62128DV30LL-70ZAI	ROCHESTER	获取价格	128KX8 STANDARD SRAM, 70ns, PDSO32, 8 X 13.40 MM, STSOP-32
CY62128DV30LL-70ZAIT	CYPRESS	获取价格	Standard SRAM, 128KX8, 70ns, CMOS, PDSO32, 8 X 13.40 MM, STSOP-32

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