Delta39K™ ISR™
CPLD Family
PRELIMINARY
Embedded Memory
Cluster Memory Initialization
Each member of the Delta39K family contains two types of
embedded memory blocks. The channel memory block is
placed at the intersection of horizontal and vertical routing
channels. Each channel memory block is 4096 bits in size and
can be configured as asynchronous or synchronous Dual Port
RAM, or synchronous FIFO. The memory organization is con-
figurable as 4Kx1, 2Kx2, 1Kx4 and 512x8. The second type of
memory block is located within each LBC and is referred to as
a cluster memory block. Each LBC contains two cluster mem-
ory blocks that are 8192 bits in size. Similar to the channel
memory blocks, the cluster memory blocks can be configured
as 8Kx1, 4Kx2, 2Kx4 and 1Kx8 and can be configured as ei-
ther asynchronous or synchronous single-port RAM.
The cluster memory powers up in an undefined state, but is set
to a user-defined known state during configuration. To facilitate
the use of look-up-table (LUT) logic and ROM applications, the
cluster memory blocks can be initialized with a given set of
data when the device is configured at power up. For LUT and
ROM applications, the user cannot write to memory blocks.
Channel Memory
The Delta39K architecture includes an embedded memory
block at each crossing point of horizontal and vertical routing
channels. The channel memory is a 4096-bit embedded mem-
ory block that can be configured as Asynchronous Dual-Port
memory, Synchronous Dual-Port memory, or Synchronous
FIFO memory.
Cluster Memory
Data, address, and control inputs to the channel memory are
driven from horizontal and vertical routing channels. All data
and FIFO logic outputs drive dedicated tracks in the horizontal
and vertical routing channels. The clocks for the channel mem-
ory block are selected from four global clocks and pin inputs
from the horizontal and vertical channels. The clock muxes
also include a polarity mux for each clock so that the user can
choose an inverted clock.
Each logic block cluster of the Delta39K contains two 8192-bit
cluster memory blocks. Figure 5 is a block diagram of the clus-
ter memory block and the interface of the cluster memory block
to the cluster PIM.
The output of the cluster memory block can be optionally reg-
istered to perform synchronous pipelining or to register asyn-
chronous read and write operations. The output registers con-
tain an asynchronous RESET which can be used in any type
of sequential logic circuits (e.g., state machines)
Dual-Port (Channel Memory) Configuration
Each port has distinct address inputs, as well as separate data
and control inputs that can be accessed simultaneously. The
inputs to the Dual-Port memory are driven from the horizontal
and vertical routing channels. The data outputs drive dedicat-
ed tracks in the routing channels. The interface to the routing
is such that Port A of the Dual-Port interfaces primarily with the
horizontal routing channel and Port B interfaces primarily with
There are four global clocks (GCLK[3:0]) and one local clock
available for the input and the output registers. The local clock
for the input registers is independent of the one used for the
output registers. The local clock is generated in the user-de-
sign in a macrocell or comes from an I/O pin
the vertical routing channel.
.
Write
Control
Logic
DIN[7:0]
ADDR[12:0]
W E
3
D
D
D
Q
Q
Q
C
C
2
8
C
1024x8
Asynchronous
SRAM
10
C
Cluster PIM
GCLK[3:0]
5:1
Local CLK
3
3
C
8
C
DOUT[7:0]
Read
Control
Logic
Q
D
C
R
RESET
2
C
GCLK[3:0]
5:1
Local CLK
3
C
C
Figure 5. Block Diagram of Cluster Memory Block
7
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