Delta39K™ ISR™
CPLD Family
PRELIMINARY
The Delta39KZ devices accept 1.8V on the V
directly. With Delta39K’s AnyVolt technology, the I/O pins can
supply pins
General Description
CC
The Delta39K family, based on a 0.18µ, 6-layer metal CMOS
logic process, offers a wide range of high-density solutions at
unparalleled system performance. The Delta39K family is de-
signed to combine the high speed, predictable timing, and
ease of use of CPLDs with the high densities and low power
of FPGAs. With devices ranging from 15,000 to 350,000 us-
able gates, the family features devices ten times the size of
previously available CPLDs. Even at these large densities, the
Delta39K family is fast enough to implement a fully synthesiz-
able 64-bit, 66-MHz PCI core.
be connected to either 1.8V, 2.5V, or 3.3V. All Delta39K devices
are 3.3V tolerant regardless of V
or V settings
CCIO
CC
Device
39KV
V
V
CCIO
CC
[4]
[4]
3.3V or 2.5V
1.8V
3.3V or 2.5V or 1.8V or 1.5V
3.3V or 2.5V or 1.8V or 1.5V
39KZ
Note:
4. For HSTL only.
Global Routing Description
The architecture is based on Logic Block Clusters (LBC) that
are connected by Horizontal and Vertical (H&V) routing chan-
nels. Each LBC features eight individual Logic Blocks (LB) and
two cluster memory blocks. Adjacent to each LBC is a channel
memory block, which can be accessed directly from the I/O
pins. Both types of memory blocks are highly configurable and
can be cascaded in width and depth. See Figure 1 for a block
diagram of the Delta39K architecture.
The routing architecture of the Delta39K is made up of hori-
zontal and vertical (H&V) routing channels. These routing
channels allow signals from each of the Delta39K architectural
components to communicate with one another. In addition to
the horizontal and vertical routing channels that interconnect
the I/O banks, channel memory blocks, and logic block clus-
ters, each LBC contains a PIM, which is used to route signals
among the logic blocks and the cluster memory blocks.
All the members of the Delta39K family maintain Cypress’s
highly regarded In-System Reprogrammability (ISR) feature,
which simplifies both design and manufacturing flows, thereby
reducing costs. The ISR feature provides the ability to recon-
figure the devices without having design changes cause pinout
or timing changes in most cases. The Cypress ISR function is
implemented through a JTAG-compliant serial interface. Data
is shifted in and out through the TDI and TDO pins respectively.
Superior routability, simple timing, and the ISR allows users to
change existing logic designs while simultaneously fixing pi-
nout assignments and maintaining system performance.
Figure 2 is a block diagram of the routing channels that inter-
face within the Delta39K architecture. The LBC is exactly the
same for every member of the Delta39K CPLD family.
Logic Block Cluster (LBC)
The Delta39K architecture consists of several logic block clus-
ters (LBCs), each of which have 8 Logic Blocks (LB) and 2
cluster memory blocks connected via a Programmable Inter-
connect Matrix (PIM™) as shown in Figure 3. Each cluster
memory block consists of 8-Kbit single-port RAM, which is
configurable as synchronous or asynchronous. The cluster
memory blocks can be cascaded with other cluster memory
blocks within the same LBC as well as other LBCs to imple-
ment larger memory functions. If a cluster memory block is not
specifically utilized by the designer, Cypress’s Warp software
can automatically use it to implement large blocks of logic.
The entire family features JTAG for ISR and boundary scan,
and is compatible with the PCI Local Bus specification, meet-
ing the electrical and timing requirements. The Delta39K fam-
ily also features user programmable bus-hold and slew rate
control capabilities on each I/O pin.
AnyVolt Interface
All LBCs interface with each other via horizontal and vertical
routing channels.
All Delta39KV devices feature an on-chip regulator, which ac-
cepts 3.3V or 2.5V on the V supply pins and steps it down
CC
to 1.8V internally, the voltage level at which the core operates.
I/O Block
LB
LB
LB
LB
LB
LB
LB
LB
72
64
Cluster
PIM
Channel memory
outputs drive
dedicated tracks in the
horizontal and vertical
routing channels
Channel
Memory
Block
Cluster
Memory
Block
Cluster
Memory
Block
72
64
H-to-V
PIM
V-to-H
PIM
Pin inputs from the I/O cells
drive dedicated tracks in the
horizontal and vertical routing
channels
Figure 2. Delta39K Routing Interface
4
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