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CY39100V256-125BBI PDF预览

CY39100V256-125BBI

更新时间: 2023-08-15 00:00:00
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
49页 715K
描述
Loadable PLD, 10ns, CMOS, PBGA256, 17 X 17 MM, 1.60 MM HEIGHT, 1 MM PITCH, FBGA-256

CY39100V256-125BBI 数据手册

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Delta39KISR™  
CPLD Family  
PRELIMINARY  
Clock Inputs  
GCLK[3:0]  
4
Logic  
Block  
0
Logic  
Block  
7
36  
16  
36  
16  
Logic  
Block  
1
Logic  
Block  
6
36  
16  
36  
16  
Logic  
Block  
2
Logic  
Block  
5
36  
16  
36  
16  
PIM  
Logic  
Block  
3
Logic  
Block  
4
36  
16  
36  
16  
Cluster  
Memory  
0
Cluster  
Memory  
1
25  
8
25  
8
CC = Carry Chain  
64 Inputs From  
Vertical Routing  
Channel  
64 Inputs From  
Horizontal Routing  
Channel  
144 Outputs to  
Horizontal and Vertical  
cluster-to-channel PIMs  
Figure 3. Delta39K Logic Block Cluster Diagram  
Logic Block (LB)  
vides two important capabilities without affecting performance:  
product term steering and product term sharing.  
The logic block is the basic building block of the Delta39K ar-  
chitecture. It consists of a product term array, an intelligent  
product-term allocator, and 16 macrocells.  
Product Term Steering  
Product term steering is the process of assigning product  
terms to macrocells as needed. For example, if one macrocell  
requires ten product terms while another needs just three, the  
product term allocator will steerten product terms to one  
macrocell and three to the other. On Delta39K devices, prod-  
uct terms are steered on an individual basis. Any number be-  
tween 1and 16 product terms can be steered to any macrocell.  
Product Term Array  
Each logic block features a 72 x 83 programmable product  
term array. This array accepts 36 inputs from the PIM. These  
inputs originate from device pins and macrocell feedbacks as  
well as cluster memory and channel memory feedbacks. Ac-  
tive LOW and active HIGH versions of each of these inputs are  
generated to create the full 72-input field. The 83 product  
terms in the array can be created from any of the 72 inputs.  
Product Term Sharing  
Product term sharing is the process of using the same product  
term among multiple macrocells. For example, if more than  
one function has one or more product terms in its equation that  
are common to other functions, those product terms are only  
programmed once. The Delta39K product term allocator al-  
lows sharing across groups of four macrocells in a variable  
fashion. The software automatically takes advantage of this  
capability so that the user does not have to intervene.  
Of the 83 product terms, 80 are for general-purpose use for the  
16 macrocells in the logic block. Two of the remaining three  
product terms in the logic block are used as asynchronous set  
and asynchronous reset product terms. The final product term  
is the Product Term clock (PTCLK) and is shared by all 16  
macrocells within a logic block.  
Product Term Allocator  
Through the product term allocator, Warp software automati-  
cally distributes the 80 product terms as needed among the 16  
macrocells in the logic block. The product term allocator pro-  
Note that neither product term sharing nor product term steer-  
ing have any effect on the speed of the product. All worst-case  
steering and sharing configurations have been incorporated in  
the timing specifications for the Delta39K devices.  
.
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