Delta39K™ ISR™
CPLD Family
PRELIMINARY
Macrocell
which drives through the circuit quickly. Figure 4 shows that the
carry chain logic within the macrocell consists of two product
terms (CPT0 and CPT1) from the PTA and an input carry-in for
carry logic. The inputs to the carry chain mux are connected
directly to the product terms in the PTA. The output of the carry
chain mux generates the carry-out for the next macrocell in the
logic block as well as the local carry input that is connected to
an input of the XOR input mux. Carry-in and a configuration bit
are inputs to an AND gate. This AND gate provides a method
of segmenting the carry chain in any macrocell in the logic
block.
Within each logic block there are 16 macrocells. Each
macrocell accepts up to 16 product terms which can be output
in either registered or combinatorial mode. Figure 4 displays
the block diagram of the macrocell. The register can be asyn-
chronously preset or asynchronously reset at the macrocell
level with the separate preset and reset product terms. Each
of these product terms features programmable polarity. This
allows the registers to be preset or reset based on an AND
expression or an OR expression.
An XOR gate in the Delta39K macrocell allows for many differ-
ent types of equations to be realized. It can be used as a po-
larity mux to implement the true or complement form of an
equation in the product term array or as a toggle to turn the D
flip-flop into a T flip-flop. The carry-chain input mux allows ad-
ditional flexibility for the implementation of different types of
logic. The macrocell can utilize the carry chain logic to imple-
ment adders, subtractors, magnitude comparators, parity tree,
or even generic XOR logic. The output of the macrocell is ei-
ther registered or combinatorial.
Macrocell Clocks
Clocking of the register is highly flexible. Four global synchro-
nous clocks (GCLK[3:0]) and a Product Term (PTCLK) clock
are available at each macrocell register. Furthermore, a clock
polarity mux within each macrocell allows the register to be
clocked on the rising or the falling edge (see macrocell dia-
gram in Figure 4).
PRESET/RESET Configurations
The macrocell register can be asynchronously preset and re-
set using the PRESET and RESET mux. Both signals are ac-
tive high and can be controlled by either of two Preset/Reset
product terms (PRC[1:0] in Figure 4) or GND. In situations
where the PRESET and RESET are active at the same time,
RESET takes priority over PRESET.
Carry Chain Logic
The Delta39K macrocell features carry chain logic which is
used for fast and efficient implementation of arithmetic opera-
tions. The carry logic connects macrocells in up to 4 logic
blocks for a total of 64 macrocells. Effective data path opera-
tions are implemented through the use of carry-in arithmetic,
Carry In
(from macrocell n-1)
PRESET
Mux
0
1
C
XOR Input
3
Carry Chain
Mux
Mux
C
CPT0
CPT1
Output Mux
C
2
To PIM
C
D PSET
C
Q
FROM PTM
Up To 16 PTs
Clock
Clock Mux
Polarity
Mux
Q
RES
GCLK[3:0]
PTCLK
3
C
C
0
1
Carry Out
(to macrocell n+1)
3
C
RESET
Mux
Figure 4. Delta39K Macrocell
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