Datasheet > CY2XP22_11

CY2XP22_11

更新时间： 2024-10-02 09:41:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
10页	270K
描述
Crystal to LVPECL Clock Generator One LVPECL output pair

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数据手册

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CY2XP22_11 数据手册

CY2XP22

Crystal to LVPECL Clock Generator

■ Pb-free 8-Pin TSSOP package

Features

■ Supply voltage: 3.3 V or 2.5 V

■ One LVPECL output pair

■ Commercial and Industrial temperature ranges

■ Selectable frequency multiplication: x2.5 or x5

■ External crystal frequency: 25.0 MHz

■ Output frequency: 62.5 MHz or 125 MHz

Functional Description

The CY2XP22 is a PLL (Phase Locked Loop) based high

performance clock generator that uses an external reference

crystal. It is specifically targeted at FibreChannel and Gigabit

Ethernet applications. It produces a selectable output frequency

that is 2.5 or 5 times the crystal frequency. With a 25 MHz crystal,

the user can select either a 62.5 MHz or 125 MHz output. It uses

Cypress’s low noise VCO technology to achieve less than 1 ps

typical RMS phase jitter. The CY2XP22 has a crystal oscillator

interface input and one LVPECL output pair.

■ Low RMS phase jitter at 125 MHz, using 25 MHz crystal

(1.875 MHz to 20 MHz): 0.4 ps (typical)

■ Phase noise at 125 MHz (typical):

Offset

1 kHz

Noise Power

–117 dBc/Hz

–126 dBc/Hz

–131 dBc/Hz

10 kHz

100 kHz

1 MHz

Logic Block Diagram

XIN

External

Crystal

CLK

CRYSTAL

OSCILLATOR

LOW -N OISE

PLL

OUTPUT

DIVIDER

CLK#

XOUT

F_SEL

Pinouts

Figure 1. Pin Diagram – 8-Pin TSSOP

VDD

VSS

XOUT

XIN

VDD

CLK

CLK#

F_SEL

Table 1. Pin Definitions – 8-Pin TSSOP

Pin Number

Pin Name

VDD

I/O Type

Description

1, 8

Power

3.3 V or 2.5 V power supply

Ground

VSS

3, 4

XOUT, XIN

F_SEL

XTAL output and input

CMOS input

Parallel resonant crystal interface

Frequency Select: see Frequency Table

Differential clock output

6,7

CLK#, CLK

LVPECL output

Cypress Semiconductor Corporation

Document #: 001-10229 Rev. *F

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 11, 2011

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