Datasheet > CY2XP306

CY2XP306

更新时间： 2024-10-02 03:12:59

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟
页数	文件大小	规格书
9页	218K
描述
High-frequency Programmable PECL Clock Generation Module

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中文翻译

获取价格

数据手册

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CY2XP306 数据手册

PRELIMINARY

CY2XP306

High-frequency Programmable PECL Clock Generation Module

• 1–133 MHz Input Frequency Range

• 62.5–500 MHz Output Frequency Range

• 36-pin VFBGA, 6 × 8 × 1 mm

• 3.3V operation

• Serially Configurable Multiply Ratios

Features

• 60 ps typical Cycle-to-Cycle Jitter

• 30 ps typical Output-Output Skew

• Phase-locked loop (PLL) multiplier select

• LVTTL or XO Input; Six LVPECL Outputs

• Selectable Output Divider (/2)

Block Diagram

QA1

FSELA

QA1#

QA2

PLL_MULT

QA2#

QA3

XIN/REF

XTAL

QA3#

PLL

OSCILLATOR

XOUT

QB1

SER CLK

QB1#

QB2

SER DATA

QB2#

QB3

QB3#

FSELB

Pin Configuration (Top View)

C Y 2X P 306 36 V FB G A P IN C O N F IG U R A T IO N

T O P V IE W

Q A1

Q B1#

VD D A

Q A1#

G N D

Q A3#

Q B1

Q A2

Q A3

Q A2#

G N D

VD D A

G N D

SER _

D ATA

VD D B

VD D A

Q B3

Q B2

SER _

C LK

N C

XO U T

Q B2#

VD D B

G N D

Q B3#

VD D A

XIN

G N D

PLL_

M U LT

M R

VD D A

FSELB

VD D B

FSELA

G N D

VD D B

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Document #: 38-07725 Rev. *A

Revised April 8, 2005

12 3 4 5 6 7...9

中文翻译

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