Datasheet > CY2XP31_11

CY2XP31_11

更新时间： 2024-10-02 09:41:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
10页	275K
描述
312.5 MHz LVPECL Clock Generator

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中文翻译

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数据手册

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CY2XP31_11 数据手册

CY2XP31

312.5 MHz LVPECL Clock Generator

Features

Functional Description

■ One LVPECL output pair

The CY2XP31 is a PLL (Phase Locked Loop) based high

performance clock generator. It is optimized to generate 10 Gb

Ethernet, SONET, and other high performance clock

frequencies. It also produces an output frequency that is 12.5

times the crystal frequency. It uses Cypress’s low noise VCO

technology to achieve less than 1 ps typical RMS phase jitter,

which meets both 10 Gb Ethernet and SONET jitter

requirements. The CY2XP31 has a crystal oscillator interface

input and one LVPECL output pair.

■ Output frequency: 312.5 MHz

■ External crystal frequency: 25 MHz

■ Low RMS phase jitter at 312.5 MHz, using 25 MHz crystal

(1.875 MHz to 20 MHz): 0.3 ps (typical)

■ Pb-free 8-Pin TSSOP package

■ Supply voltage: 3.3 V or 2.5 V

■ Commercial and industrial temperature ranges

Logic Block Diagram

XIN

CLK

External

Crystal

CRYSTAL

OSCILLATOR

PHASE

DETECTOR

VCO

CLK#

XOUT

/25

Pinouts

Figure 1. Pin Diagram – 8-Pin TSSOP

VDD

VSS

XOUT

XIN

VDD

CLK

CLK#

Table 1. Pin Definition – 8-Pin TSSOP

Pin Number

Pin Name

VDD

I/O Type

Description

1, 8

Power

3.3 V or 2.5 V power supply. All supply current flows through pin 1

VSS

Ground

3, 4

XOUT, XIN

XTAL Output and Input

CMOS Input

Parallel resonant crystal interface

Output enable. When HIGH, the output is enabled. When LOW, the

output is high impedance

6,7

CLK#, CLK

LVPECL Output

Differential clock output

Cypress Semiconductor Corporation

Document #: 001-06385 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 7, 2011

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