CY2XP24

更新时间： 2024-10-02 09:41:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
12页	392K
描述
Crystal to LVPECL Clock Generator One LVPECL Output Pair

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CY2XP24 数据手册

CY2XP24

Crystal to LVPECL Clock Generator

Features

Functional Description

■ One LVPECL Output Pair

The CY2XP24 is a PLL (phase locked loop) based high

performance clock generator. It is optimized to generate 10 Gb

Ethernet, Fibre Channel, and other high performance clock

frequencies. It produces an output frequency that is either 6.25

times or 7.5 times the crystal frequency. It uses Cypress’s low

noise VCO technology to achieve low phase jitter, that meets

both 10 Gb Ethernet, Fibre Channel, and SATA jitter

requirements. The CY2XP24 has a crystal oscillator interface

input and one LVPECL output pair.

■ Selectable output frequency: 156.25 MHz or 187.5 MHz

■ External crystal frequency: 25 MHz

■ Low root mean square (RMS) phase jitter at 156.25 MHz, using

25 MHz crystal (1.875 MHz to 20 MHz): 0.33 ps (typical)

■ Pb-free 8-Pin thin shrunk small outline package (TSSOP)

Package

■ Supply voltage: 3.3 V or 2.5 V

■ Commercial and industrial temperature ranges

Logic Block Diagram

XIN

CLK

External

Crystal

CRYSTAL

OSCILLATOR

PHASE

DETECTOR

VCO

CLK#

XOUT

0 = /25

1 = /30

F_SEL

Cypress Semiconductor Corporation

Document #: 001-15705 Rev. *G

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised April 7, 2011

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