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CY2SSTV16857ZIT

更新时间： 2024-11-20 20:26:39
品牌 Logo 应用领域
芯科 - SILICON 光电二极管逻辑集成电路触发器电视
页数 文件大小 规格书
7页 86K
描述
D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.240 INCH, MO-153, TSSOP2-48

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CY2SSTV16857ZIT 技术参数

生命周期：Obsolete零件包装代码：TSSOP
包装说明：0.240 INCH, MO-153, TSSOP2-48针数：48
Reach Compliance Code：unknownHTS代码：8542.39.00.01
风险等级：5.1Is Samacsys：N
系列：SSTVJESD-30 代码：R-PDSO-G48
长度：12.4965 mm逻辑集成电路类型：D FLIP-FLOP
位数：14功能数量：1
端子数量：48最高工作温度：85 °C
最低工作温度：-40 °C输出极性：TRUE
封装主体材料：PLASTIC/EPOXY封装代码：TSSOP
封装形状：RECTANGULAR封装形式：SMALL OUTLINE, THIN PROFILE, SHRINK PITCH
传播延迟（tpd）：2.8 ns认证状态：Not Qualified
座面最大高度：1.1 mm最大供电电压 (Vsup)：2.7 V
最小供电电压 (Vsup)：2.3 V标称供电电压 (Vsup)：2.5 V
表面贴装：YES温度等级：INDUSTRIAL
端子形式：GULL WING端子节距：0.5 mm
端子位置：DUAL触发器类型：POSITIVE EDGE
宽度：6.096 mm最小 fmax：280 MHz
Base Number Matches：1

CY2SSTV16857ZIT 数据手册

 浏览型号CY2SSTV16857ZIT的Datasheet PDF文件第2页浏览型号CY2SSTV16857ZIT的Datasheet PDF文件第3页浏览型号CY2SSTV16857ZIT的Datasheet PDF文件第4页浏览型号CY2SSTV16857ZIT的Datasheet PDF文件第5页浏览型号CY2SSTV16857ZIT的Datasheet PDF文件第6页浏览型号CY2SSTV16857ZIT的Datasheet PDF文件第7页 
CY2SSTV16857  
14-Bit Registered Buffer PC2700-/PC3200-Compliant  
When RESET is LOW, the differential input receivers are  
disabled, and undriven (floating) data, clock, and REF voltage  
inputs are allowed. In addition, when RESET is LOW, all  
registers are reset and all outputs force to the LOW state. The  
LVCMOS RESET input must always be held at a valid logic  
HIGH or LOW level.  
Features  
• Differential Clock Inputs up to 280 MHz  
• Supports LVTTL switching levels on the RESET pin  
• Output drivers have controlled edge rates, so no  
external resistors are required  
To ensure defined outputs from the register before a stable  
clock has been supplied, RESET must be held in the LOW  
state during power-up.  
• Two KV ESD protection  
• Latch-upperformanceexceeds 100 mA: JESD78, Class II  
In the DDR registered DIMM application, RESET is specified  
to be completely asynchronous with respect to CLK and CLK.  
Therefore, no timing relationship can be guaranteed between  
the two. When entering reset, the register will be cleared and  
the outputs will be driven LOW quickly, relative to the time to  
disable the differential input receivers, thus ensuring no  
glitches on the output. However, when coming out of reset, the  
register will become active quickly, relative to the time to  
enable the differential input receivers. As long as the data  
inputs are low, and the clock is stable during the time from the  
LOW-to-HIGH transition of RESET until the input receivers are  
fully enabled, the design must ensure that the outputs will  
remain LOW.  
• Conforms to JEDEC STD (JESD82-3) for buffered DDR  
DIMMs  
• 48-pin TSSOP  
Description  
This 14-bit registered buffer is designed specifically for 2.3V to  
2.7V VDD operation and is characterized for operation from  
0°C to + 85°C.  
All inputs are compatible with the JEDEC Standard for  
SSTL_2, except the LVCMOS reset (RESET) input. All outputs  
are SSTL_2, Class II-compatible.  
The SSTV16857 operates from a differential clock (CLK and  
CLK). Data is measured at the crossing of CLK going HIGH,  
and CLK going LOW.  
Pin Configuration  
Block Diagram  
Q1  
Q2  
VSS  
VDDQ  
Q3  
Q4  
Q5  
VSS  
VDDQ  
Q6  
D1  
1
2
3
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
RESET  
D2  
VSS  
VDD  
D3  
D4  
D5  
4
5
6
CLK  
CLK  
7
8
9
D6  
VREF  
D7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CLK  
CLK  
VDD  
VSS  
VREF  
RESET  
D8  
D1  
Q7  
1D  
VDDQ  
VSS  
Q8  
C1  
Q1  
Q9  
VDDQ  
VSS  
Q10  
Q11  
Q12  
VDDQ  
VSS  
Q13  
Q14  
R
D9  
D10  
D11  
D12  
VDD  
VSS  
D13  
D14  
To 13 Other Channels  
Rev 1.0, November 21, 2006  
Page 1 of 7  
www.SpectraLinear.com  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
1234567

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与CY2SSTV16857ZIT相关器件

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CY2SSTV16857ZXC CYPRESS

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 		14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXC SPECTRALINEAR

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 		14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXC SILICON

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 		D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.
CY2SSTV16857ZXCT SPECTRALINEAR

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 		14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXCT SILICON

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 		D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.
CY2SSTV16857ZXCT CYPRESS

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 		14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXI SPECTRALINEAR

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 		14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXI CYPRESS

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 		14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXIT SPECTRALINEAR

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 		14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXIT CYPRESS

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 		14-Bit Registered Buffer PC2700-/PC3200-Compliant

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