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CY2SSTV16857ZXCT

更新时间： 2024-11-24 03:10:11
品牌 Logo 应用领域
赛普拉斯 - CYPRESS PC
页数 文件大小 规格书
8页 144K
描述
14-Bit Registered Buffer PC2700-/PC3200-Compliant

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CY2SSTV16857ZXCT 数据手册

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CY2SSTV16857  
14-Bit Registered Buffer  
PC2700-/PC3200-Compliant  
When RESET is LOW, the differential input receivers are  
disabled, and undriven (floating) data, clock, and REF voltage  
inputs are allowed. In addition, when RESET is LOW, all  
registers are reset and all outputs force to the LOW state. The  
LVCMOS RESET input must always be held at a valid logic  
HIGH or LOW level.  
Features  
• Differential Clock Inputs up to 280 MHz  
• Supports LVTTL switching levels on the RESET pin  
• Output drivers have controlled edge rates, so no  
external resistors are required  
To ensure defined outputs from the register before a stable  
clock has been supplied, RESET must be held in the LOW  
state during power-up.  
• Two KV ESD protection  
• Latch-upperformanceexceeds 100 mA: JESD78, Class II  
In the DDR registered DIMM application, RESET is specified  
to be completely asynchronous with respect to CLK and CLK.  
Therefore, no timing relationship can be guaranteed between  
the two. When entering reset, the register will be cleared and  
the outputs will be driven LOW quickly, relative to the time to  
disable the differential input receivers, thus ensuring no  
glitches on the output. However, when coming out of reset, the  
register will become active quickly, relative to the time to  
enable the differential input receivers. As long as the data  
inputs are low, and the clock is stable during the time from the  
LOW-to-HIGH transition of RESET until the input receivers are  
fully enabled, the design must ensure that the outputs will  
remain LOW.  
• Conforms to JEDEC STD (JESD82-3) for buffered DDR  
DIMMs  
• 48-pin TSSOP  
Description  
This 14-bit registered buffer is designed specifically for 2.3V to  
2.7V VDD operation and is characterized for operation from  
0°C to + 85°C.  
All inputs are compatible with the JEDEC Standard for  
SSTL_2, except the LVCMOS reset (RESET) input. All outputs  
are SSTL_2, Class II-compatible.  
The SSTV16857 operates from a differential clock (CLK and  
CLK). Data is measured at the crossing of CLK going HIGH,  
and CLK going LOW.  
Pin Configuration  
Block Diagram  
Q1  
Q2  
VSS  
VDDQ  
Q3  
D1  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
RESET  
2
D2  
3
VSS  
VDD  
D3  
4
CLK  
CLK  
5
Q4  
Q5  
6
D4  
D5  
7
VSS  
VDDQ  
Q6  
D6  
8
VREF  
9
D7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CLK  
CLK  
VDD  
VSS  
VREF  
RESET  
D8  
D1  
Q7  
1D  
VDDQ  
VSS  
Q8  
C1  
Q1  
Q9  
VDDQ  
VSS  
Q10  
Q11  
Q12  
VDDQ  
VSS  
Q13  
Q14  
R
D9  
D10  
D11  
D12  
VDD  
VSS  
D13  
D14  
To 13 Other Channels  
Cypress Semiconductor Corporation  
•
3901 North First Street  
•
San Jose, CA 95134  
•
408-943-2600  
Document #: 38-07443 Rev. *D  
Revised January 12, 2005  
12345678

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