5秒后页面跳转
捷配首页

Datasheet > CY2SSTV16857ZXCT
CY2SSTV16857ZXCT PDF预览

CY2SSTV16857ZXCT

更新时间： 2024-11-24 03:10:11
品牌 Logo 应用领域
SPECTRALINEAR PC
页数 文件大小 规格书
7页 91K
描述
14-Bit Regstered Buffer PC2700-/PC3200-Compliant

阅读下载

中文翻译

获取价格

CY2SSTV16857ZXCT 数据手册

 浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第2页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第3页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第4页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第5页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第6页浏览型号CY2SSTV16857ZXCT的Datasheet PDF文件第7页 
CY2SSTV16857  
14-Bit Registered Buffer PC2700-/PC3200-Compliant  
When RESET is LOW, the differential input receivers are  
disabled, and undriven (floating) data, clock, and REF voltage  
Features  
• Differential Clock Inputs up to 280 MHz  
inputs are allowed. In addition, when RESET is LOW, all  
registers are reset and all outputs force to the LOW state. The  
LVCMOS RESET input must always be held at a valid logic  
HIGH or LOW level.  
• Supports LVTTL switching levels on the RESET pin  
• Output drivers have controlled edge rates, so no  
external resistors are required  
To ensure defined outputs from the register before a stable  
clock has been supplied, RESET must be held in the LOW  
state during power-up.  
• Two KV ESD protection  
• Latch-upperformanceexceeds 100 mA: JESD78, Class II  
In the DDR registered DIMM application, RESET is specified  
to be completely asynchronous with respect to CLK and CLK.  
Therefore, no timing relationship can be guaranteed between  
the two. When entering reset, the register will be cleared and  
the outputs will be driven LOW quickly, relative to the time to  
disable the differential input receivers, thus ensuring no  
glitches on the output. However, when coming out of reset, the  
register will become active quickly, relative to the time to  
enable the differential input receivers. As long as the data  
inputs are low, and the clock is stable during the time from the  
LOW-to-HIGH transition of RESET until the input receivers are  
fully enabled, the design must ensure that the outputs will  
remain LOW.  
• Conforms to JEDEC STD (JESD82-3) for buffered DDR  
DIMMs  
• 48-pin TSSOP  
Description  
This 14-bit registered buffer is designed specifically for 2.3V to  
2.7V VDD operation and is characterized for operation from  
0°C to + 85°C.  
All inputs are compatible with the JEDEC Standard for  
SSTL_2, except the LVCMOS reset (RESET) input. All outputs  
are SSTL_2, Class II-compatible.  
The SSTV16857 operates from a differential clock (CLK and  
CLK). Data is measured at the crossing of CLK going HIGH,  
and CLK going LOW.  
Pin Configuration  
Block Diagram  
Q1  
Q2  
D1  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
RESET  
2
D2  
VSS  
VDDQ  
Q3  
3
VSS  
VDD  
D3  
4
CLK  
CLK  
5
Q4  
6
D4  
Q5  
D5  
7
VSS  
VDDQ  
Q6  
D6  
8
VREF  
9
D7  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
CLK  
CLK  
VDD  
VSS  
VREF  
RESET  
D8  
D1  
Q7  
1D  
VDDQ  
VSS  
Q8  
C1  
Q1  
Q9  
VDDQ  
VSS  
Q10  
Q11  
Q12  
VDDQ  
VSS  
Q13  
Q14  
R
D9  
D10  
D11  
D12  
VDD  
VSS  
D13  
D14  
To 13 Other Channels  
Rev 1.0, November 21, 2006  
Page 1 of 7  
www.SpectraLinear.com  
2200 Laurelwood Road, Santa Clara, CA 95054  
Tel:(408) 855-0555 Fax:(408) 855-0550  
1234567

中文翻译

下载PDF

与CY2SSTV16857ZXCT相关器件

型号 品牌 获取价格 描述 数据表
CY2SSTV16857ZXI SPECTRALINEAR

获取价格

 		14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXI CYPRESS

获取价格

 		14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXIT SPECTRALINEAR

获取价格

 		14-Bit Regstered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXIT CYPRESS

获取价格

 		14-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16857ZXIT SILICON

获取价格

 		D Flip-Flop, SSTV Series, 1-Func, Positive Edge Triggered, 14-Bit, True Output, PDSO48, 0.
CY2SSTV16859 CYPRESS

获取价格

 		13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16859 SPECTRALINEAR

获取价格

 		13-Bit to 26-Bit Registered Buffer PC2700-/PC3100-Compliant
CY2SSTV16859LFC SPECTRALINEAR

获取价格

 		13-Bit to 26-Bit Registered Buffer PC2700-/PC3100-Compliant
CY2SSTV16859LFC CYPRESS

获取价格

 		13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant
CY2SSTV16859LFCT CYPRESS

获取价格

 		13-Bit to 26-Bit Registered Buffer PC2700-/PC3200-Compliant

与CY2SSTV16857ZXCT相关文章

您还可以找


热门产品
PCB打样/小批量
铝基板
BOM智能配单
PCBA制造
钣金
精密CNC
模具注塑
薄膜开关
精选活动
PCBA打样特惠
四六层板品质升级
铝基板品质升级
一体化电子制造
DFM下载
服务支持
企业认证
产品展示
工厂展示
工艺能力
积分商城
关于捷配
捷配简介
企业文化
公司动态
人才招聘
联系我们
帮助中心
下单流程
付款流程
开票流程
常见问题
全球PCB制造服务专线 400-613-0088

工作时间：9:00-21:00

CEO邮箱：ceo@jiepei.com

投诉邮箱：tousu@jiepei.com

捷配网-微信公众号 微信公众号
捷配网-微信公众号 抖音公众号
资质认证：
合作快递：
支付方式：
Copyright © 2024 Jiepei.com Inc. All Rights Reserved. 版权所有:杭州捷配信息科技有限公司 浙公网安备 33010502006866号 浙ICP备10014259号-119 营业执照ICP证