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CY2907SL-XXXT PDF预览

CY2907SL-XXXT

更新时间: 2024-11-02 03:09:43
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟发生器可编程只读存储器电动程控只读存储器
页数 文件大小 规格书
11页 354K
描述
Single-PLL General Purpose EPROM Programmable Clock Generator

CY2907SL-XXXT 数据手册

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CY2907  
Single-PLL General Purpose EPROM  
Programmable Clock Generator  
Benefits  
Features  
• Single phase locked loop (PLL) architecture  
• EPROM programmability  
• Generates a custom frequency from an external source  
• Easy customization and fast turnaround  
• Factory-programmable (CY2907, CY2907I) or  
• Programming support available for all opportunities  
field-programmable (CY2907F, CY2907FI) device options  
• Provides clocking requirements from a single device  
• Meets critical industry-standard timing requirements  
• Supports low-power applications  
• Up to two configurable outputs  
• Low skew, low jitter, high accuracy outputs  
• Power management (power down, OE)  
• Frequency select option  
• Up to 16 user-selectable frequencies  
• Supports industry-standard design platforms  
• Industry-standard packaging saves on board space  
• Configurable 5V or 3.3V operation  
• 8-pin or 14-pin SOIC packages  
Selector Guide  
Part Number Outputs  
Input Frequency Range  
Output Frequency Range  
Specifics  
CY2907  
2
2
2
2
10 MHz–25 MHz (external crystal) 500 kHz–130 MHz (5V)  
Factory Programmable  
Commercial Temperature  
500 kHz–100 MHz (3.3V)  
10 MHz–25 MHz (external crystal) 500 kHz–100 MHz (5V)  
1 MHz–30 MHz (reference clock)  
CY2907I  
Factory Programmable  
Industrial Temperature  
500 kHz–80 MHz (3.3V)  
1 MHz–30 MHz (reference clock)  
CY2907F8  
CY2907F14  
10 MHz–25 MHz (external crystal) 500 kHz–100 MHz (5V)  
Field Programmable  
Commercial Temperature  
500 kHz–80 MHz (3.3V)  
1 MHz–30 MHz (reference clock)  
CY2907F8I  
CY2907F14I  
10 MHz–25 MHz (external crystal) 500 kHz–90 MHz (5V)  
Field Programmable  
Industrial Temperature  
500 kHz–66.66 MHz (3.3V)  
1 MHz–30 MHz (reference clock)  
Logic Block Diagram  
Pin Configurations  
Top View  
OEA  
OER  
14-Pin SOIC  
14  
13  
12  
11  
10  
9
S1  
S2  
S3  
S0  
1
2
3
4
5
6
7
REFCLK  
CLKA  
REFCLK  
PD  
V
DD  
Output  
Multiplexer  
and  
Dividers  
V
SS  
CLKA  
XTALIN  
OSC.  
V
SS  
OEA  
OER  
PLL  
PD  
XTALOUT  
XTALIN  
8
XTALOUT  
EPROM  
Table  
Configuration  
EPROM  
and Test Logic  
8-Pin SOIC  
S0  
S1  
S0  
REFCLK  
1
2
3
4
8
7
6
5
V
SS  
V
DD  
XTALIN  
CLKA  
S1  
XTALOUT  
S2  
S3  
Cypress Semiconductor Corporation  
Document #: 38-07137 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised May 21, 2007  
[+] Feedback  

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