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CY29350AI PDF预览

CY29350AI

更新时间: 2024-09-24 04:13:19
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 时钟驱动器
页数 文件大小 规格书
7页 187K
描述
2.5V or 3.3V, 200-MHz, 9-Output Clock Driver

CY29350AI 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFP包装说明:TQFP,
针数:32Reach Compliance Code:unknown
ECCN代码:EAR99HTS代码:8542.39.00.01
Factory Lead Time:1 week风险等级:5.78
其他特性:ALSO OPERATES AT 3.3V SUPPLYJESD-30 代码:S-PQFP-G32
JESD-609代码:e0长度:7 mm
湿度敏感等级:3端子数量:32
最高工作温度:85 °C最低工作温度:-40 °C
最大输出时钟频率:200 MHz封装主体材料:PLASTIC/EPOXY
封装代码:TQFP封装形状:SQUARE
封装形式:FLATPACK, THIN PROFILE峰值回流温度(摄氏度):240
主时钟/晶体标称频率:31.25 MHz认证状态:Not Qualified
座面最大高度:1.2 mm最大供电电压:2.625 V
最小供电电压:2.375 V标称供电电压:2.5 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:TIN LEAD
端子形式:GULL WING端子节距:0.8 mm
端子位置:QUAD处于峰值回流温度下的最长时间:30
宽度:7 mmuPs/uCs/外围集成电路类型:CLOCK GENERATOR, OTHER
Base Number Matches:1

CY29350AI 数据手册

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CY29350  
2.5V or 3.3V, 200-MHz, 9-Output Clock Driver  
Features  
Functional Description  
• Output frequency range: 25 MHz to 200 MHz  
• Input frequency range: 6.25 MHz to 31.25 MHz  
• 2.5V or 3.3V operation  
The CY29350 is a low-voltage high-performance 200-MHz  
PLL-based clock driver designed for high speed clock distri-  
bution applications.  
The CY29350 features Xtal and LVCMOS reference clock  
inputs and provides nine outputs partitioned in four banks of 1,  
1, 2, and 5 outputs. Bank A divides the VCO output by 2 or 4  
while the other banks divide by 4 or 8 per SEL(A:D) settings,  
see . These dividers allow output to input ratios of 16:1, 8:1,  
4:1, and 2:1. Each LVCMOS compatible output can drive 50Ω  
series or parallel terminated transmission lines. For series  
terminated transmission lines, each output can drive one or  
two traces giving the device an effective fanout of 1:18.  
The PLL is ensured stable given that the VCO is configured to  
run between 200 MHz to 500 MHz. This allows a wide range  
of output frequencies from 25 MHz to 200 MHz. The internal  
VCO is running at multiples of the input reference clock set by  
the feedback divider, see Table 1.  
• Split 2.5V/3.3V outputs  
• ±2.5% max Output duty cycle variation  
• Nine Clock outputs: Drive up to 18 clock lines  
• Two reference clock inputs: Xtal or LVCMOS  
• 150-ps max output-output skew  
• Phase-locked loop (PLL) bypass mode  
• Spread Aware™  
• Output enable/disable  
• Pin-compatible with MPC9350  
• Industrial temperature range: –40°C to +85°C  
• 32-pin 1.0mm TQFP package  
When PLL_EN is LOW, PLL is bypassed and the reference  
clock directly feeds the output dividers. This mode is fully static  
and the minimum input clock frequency specification does not  
apply.  
Pin Configuration  
Block Diagram  
SELA  
PLL_EN  
REF_SEL  
TCLK  
VCO  
Phase  
Detector  
QA  
QB  
÷2 / ÷4  
XIN  
200 -  
OSC  
XOUT  
500MHz  
AVDD  
FB_SEL  
SELA  
1
2
3
4
5
6
7
8
24  
23  
22  
21  
20  
19  
18  
17  
QC0  
VDDQC  
QC1  
VSS  
QD0  
VDDQD  
QD1  
VSS  
÷4 / ÷8  
÷4 / ÷8  
LPF  
÷16 / ÷32  
SELB  
CY29350  
SELC  
SELD  
AVSS  
XOUT  
FB_SEL  
SELB  
QC0  
QC1  
SELC  
QD0  
QD1  
÷4 / ÷8  
SELD  
QD2  
QD3  
QD4  
OE#  
Cypress Semiconductor Corporation  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Document #: 38-07474 Rev. *A  
Revised July 26, 2004  

CY29350AI 替代型号

型号 品牌 替代类型 描述 数据表
CY29350AXIT CYPRESS

完全替代

2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock li
CY29350AXI CYPRESS

功能相似

2.5 V or 3.3 V, 200-MHz, 9-Output Clock Driver Nine Clock outputs: Drive up to 18 clock li
CY29350AIT CYPRESS

功能相似

2.5V or 3.3V, 200-MHz, 9-Output Clock Driver

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