Datasheet > CY2309ESXC-1H

CY2309ESXC-1H

更新时间： 2024-11-21 03:00:47

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
17页	383K
描述
PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 0.150 INCH, LEAD FREE, MS-012, SOIC-16

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CY2309ESXC-1H 数据手册

CY2305

CY2309

Low-Cost 3.3V Zero Delay Buffer

Features

Functional Description

■ 10MHzto100-/133MHzoperatingrange,compatiblewithCPU

and PCI bus frequencies

The CY2309 is a low-cost 3.3V zero delay buffer designed to

distribute high-speed clocks and is available in a 16-pin SOIC or

TSSOP package. The CY2305 is an 8-pin version of the

CY2309. It accepts one reference input, and drives out five

low-skew clocks. The -1H versions of each device operate at up

to 100-/133 MHz frequencies, and have higher drive than the -1

devices. All parts have on-chip PLLs which lock to an input clock

on the REF pin. The PLL feedback is on-chip and is obtained

from the CLKOUT pad.

■ Zero input-output propagation delay

■ 60 ps typical cycle-to-cycle jitter (high drive)

■ Multiple low-skew outputs

❐ 85 ps typical output-to-output skew

❐ One input drives five outputs (CY2305)

❐ One input drives nine outputs, grouped as 4 + 4 + 1 (CY2309)

The CY2309 has two banks of four outputs each, which can be

controlled by the Select inputs as shown in the “Select Input

Decoding” table on page 3. If all output clocks are not required,

BankB can be three-stated. The select inputs also allow the input

clock to be directly applied to the outputs for chip and system

testing purposes.

■ Compatible with Pentium-based systems

■ Test Mode to bypass phase-locked loop (PLL) (CY2309 only

[see “Select Input Decoding” on page 3])

■ Available in space-saving 16-pin 150-mil SOIC or 4.4-mm

TSSOPpackages(CY2309), and8-pin, 150-milSOICpackage

(CY2305)

The CY2305 and CY2309 PLLs enter a power down mode when

there are no rising edges on the REF input. In this state, the

outputs are three-stated and the PLL is turned off, resulting in

less than 12.0 μA of current draw for commercial temperature

devices and 25.0 μA for industrial temperature parts. The

CY2309 PLL shuts down in one additional case as shown in the

table below.

■ 3.3V operation

■ Industrial temperature available

Multiple CY2305 and CY2309 devices can accept the same input

clock and distribute it. In this case, the skew between the outputs

of two devices is guaranteed to be less than 700 ps.

The CY2305/CY2309 is available in two/three different configu-

rations, as shown in the ordering information (page 12). The

CY2305-1/CY2309-1 is the base part. The CY2305-1H/

CY2309-1H is the high-drive version of the -1, and its rise and

fall times are much faster than the -1s.

Logic Block Diagram

CLKOUT

MUX

PLL

REF

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKB2

CLKB3

CLKB4

Select Input

Decoding

Cypress Semiconductor Corporation

Document #: 38-07140 Rev. *H

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised July 23, 2008

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与CY2309ESXC-1H相关器件

型号	品牌	获取价格	描述	数据表
CY2309ESXC-1T	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309ESXI-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309EZXC-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309EZXI-1H	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309EZXI-1HT	CYPRESS	获取价格	PLL Based Clock Driver, 2309 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2309NZ	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZ_08	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSC-1H	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSC-1HT	CYPRESS	获取价格	Nine-Output 3.3V Buffer
CY2309NZSI-1H	CYPRESS	获取价格	Nine-Output 3.3V Buffer

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