Datasheet > CY2308AZI-2T

CY2308AZI-2T

更新时间： 2024-11-21 03:53:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		光电二极管
页数	文件大小	规格书
8页	69K
描述
PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16, 4.40 MM, TSSOP-16

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CY2308AZI-2T 数据手册

CY2308A

Eight-Output, 200-MHz Zero Delay Buffer

Features

Functional Description

• 50-MHz to 200-MHz operating range

The CY2308A is a high-performance 200-MHz zero delay

buffer designed for high-speed clock distribution. The

• 650-ps Total Timing Budget (TTB ) window

• Multiple configurations (see Table 2)

• Eight low-skew outputs

integrated PLL is designed for low jitter and optimized for noise

rejection. These parameters are critical for reference clock

distribution in systems using high-performance ASICs and

microprocessors. The CY2308A PLL feedback is external and

is required to be driven into the FBK pin using anyone of the

outputs.

— Output-output skew < 200 ps

— Device-device skew < 500 ps

• Input-output skew < 250 ps

• Three-stateable outputs

The device features a guaranteed maximum TTB window

specifying all occurrences of output clocks with respect to the

input reference clock across variations in output frequency,

supply voltage, operating temperature, input edge rate, and

process.

• < 50-µA shutdown current

• Phase-locked loop (PLL) bypass mode (see Table 1)

• Spread Aware

The CY2308A has two banks of four outputs each that can be

controlled by the Select inputs as shown in Table 1. If all output

clocks are not required, Bank B can be three-stated. The

select inputs also allow the input clock to be directly applied to

the output for chip and system testing purposes.

• 16-pin TSSOP

• 3.3V operation

• Commercial/Industrial temperature

The CY2308A PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

50 µA of current draw. The PLL shuts down in two additional

cases, as shown in Table 1.

The CY2308A is available in five different configurations, as

shown in Table 2. The CY2308A–1 is the base part with the

output frequencies equal to the reference if there is no divider

in the feedback path. The CY2308A–1H is the high-drive

version of the –1 with faster rise and fall times.

The CY2308A–2 allows the user to obtain 1X / ½X frequencies

on each output bank. The exact configuration and output

frequencies depends on which output drives FBK.

Pin Configuration

Block Diagram

TSSOP

Top View

FBK

PLL

REF

MUX

REF

FBK

CLKA1

CLKA2

CLKA3

CLKA4

CLKB1

CLKA1

CLKA2

CLKB2

GND

CLKA3

CLKA4

CLKB3

Select Input

Decoding

CLKB4

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2)

Cypress Semiconductor Corporation

Document #: 38-07377 Rev. *C

•

3901 North First Street

•

San Jose, CA 95134

•

408-943-2600

Revised March 5, 2003

12 3 4 5 6 7 8

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与CY2308AZI-2T相关器件

型号	品牌	获取价格	描述	数据表
CY2308SC-1	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-1H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-1HT	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-1T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-2	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-2T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-3	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-3T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-4	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SC-4T	CYPRESS	获取价格	3.3V Zero Delay Buffer

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