CY2308SI-4

更新时间： 2024-11-23 22:25:07

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟驱动器逻辑集成电路光电二极管
页数	文件大小	规格书
14页	203K
描述
3.3V Zero Delay Buffer

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CY2308SI-4 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	0.150 INCH, MS-012, SOIC-16	针数：	16
Reach Compliance Code：	not_compliant	HTS代码：	8542.39.00.01
Factory Lead Time：	1 week	风险等级：	5.01
Is Samacsys：	N	系列：	2308
输入调节：	STANDARD	JESD-30 代码：	R-PDSO-G16
JESD-609代码：	e0	长度：	9.893 mm
逻辑集成电路类型：	PLL BASED CLOCK DRIVER	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	电源：	3.3 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.2 ns
座面最大高度：	1.727 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.9 mm
最小 fmax：	133.3 MHz	Base Number Matches：	1

CY2308SI-4 数据手册

1CY2308

CY2308

3.3V Zero Delay Buffer

The CY2308 has two banks of four outputs each, which can

be controlled by the Select inputs as shown in the table “Select

Input Decoding.” If all output clocks are not required, Bank B

can be three-stated. The select inputs also allow the input

clock to be directly applied to the output for chip and system

testing purposes.

Features

• Zero input-output propagation delay, adjustable by

capacitive load on FBK input

• Multiple configurations, see “Available CY2308

Configurations” table

• Multiple low-skew outputs

— Output-output skew less than 200 ps

— Device-device skew less than 700 ps

The CY2308 PLL enters a power-down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off, resulting in less than

50 µA of current draw. The PLL shuts down in two additional

cases as shown in the “Select Input Decoding” table.

Multiple CY2308 devices can accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is guaranteed to be less than 700 ps.

The CY2308 is available in five different configurations, as

shown in the “Available CY2308 Configurations” table on page

2. The CY2308–1 is the base part, where the output

frequencies equal the reference if there is no counter in the

feedback path. The CY2308–1H is the high-drive version of

the –1, and rise and fall times on this device are much faster.

— Two banks of four outputs, three-stateable by two

select inputs

• 10-MHz to 133-MHz operating range

• Low jitter, less than 200 ps cycle-cycle (–1, –1H, –4, –5H)

• Space-saving 16-pin 150-mil SOIC package or 16-pin

TSSOP

• 3.3V operation

• Industrial Temperature available

The CY2308–2 allows the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depends on which output drives the

feedback pin. The CY2308–3 allows the user to obtain 4X and

2X frequencies on the outputs.

The CY2308–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile, and can be used

in a variety of applications.

Functional Description

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute

high-speed clocks in PC, workstation, datacom, telecom, and

other high-performance applications.

The part has an on-chip PLL which locks to an input clock

presented on the REF pin. The PLL feedback is required to be

driven into the FBK pin, and can be obtained from one of the

outputs. The input-to-output skew is guaranteed to be less

than 350 ps, and output-to-output skew is guaranteed to be

less than 200 ps.

The CY2308–5H is a high-drive version with REF/2 on both

banks.

Pin Configuration

Block Diagram

FBK

PLL

SOIC

REF

MUX

Top View

CLKA1

CLKA2

CLKA3

CLKA4

REF

CLKA1

FBK

Extra Divider (–3, –4)

Extra Divider (–5H)

CLKA4

CLKA3

V_DD

CLKA2

V_DD

GND

CLKB1

Select Input

CLKB4

CLKB3

Decoding

CLKB2

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2, –3)

Cypress Semiconductor Corporation

•

3901 North First Street

•

San Jose

•

CA 95134

•

408-943-2600

Document #: 38-07146 Rev. *C

Revised June 16, 2004

12 3 4 5 6 7...14

中文翻译

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CY2308SI-4 替代型号

型号	品牌	替代类型	描述	数据表
CY2308SXI-4T	CYPRESS	完全替代	3.3V Zero Delay Buffer
CY2308SXI-4	CYPRESS	完全替代	3.3V Zero Delay Buffer
CY2308SXI-3	CYPRESS	完全替代	3.3V Zero Delay Buffer

与CY2308SI-4相关器件

型号	品牌	获取价格	描述	数据表
CY2308SI-4T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SI-5H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SI-5HT	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308SXC-1	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SXC-1	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2308SXC-1H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SXC-1H	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2308SXC-1HT	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SXC-1HT	INFINEON	获取价格	3.3V Zero Delay Buffer
CY2308SXC-1T	CYPRESS	获取价格	3.3V Zero Delay Buffer

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