Datasheet > CY2308SI-2T

CY2308SI-2T

更新时间： 2024-11-20 03:12:31

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		/
页数	文件大小	规格书
15页	367K
描述
3.3V Zero Delay Buffer

阅读下载

中文翻译

获取价格

技术参数
数据手册

如果您发现信息不准确，欢迎纠错

CY2308SI-2T 技术参数

是否无铅：	含铅	是否Rohs认证：	不符合
生命周期：	Obsolete	零件包装代码：	SOIC
包装说明：	SOP, SOP16,.25	针数：	16
Reach Compliance Code：	not_compliant	ECCN代码：	EAR99
HTS代码：	8542.31.00.01	风险等级：	5.61
系列：	2308	输入调节：	STANDARD
JESD-30 代码：	R-PDSO-G16	JESD-609代码：	e0
长度：	9.893 mm	逻辑集成电路类型：	PLL BASED CLOCK DRIVER
最大I（ol）：	0.008 A	湿度敏感等级：	3
功能数量：	1	反相输出次数：
端子数量：	16	实输出次数：	8
最高工作温度：	85 °C	最低工作温度：	-40 °C
输出特性：	3-STATE	封装主体材料：	PLASTIC/EPOXY
封装代码：	SOP	封装等效代码：	SOP16,.25
封装形状：	RECTANGULAR	封装形式：	SMALL OUTLINE
峰值回流温度（摄氏度）：	240	电源：	3.3 V
认证状态：	Not Qualified	Same Edge Skew-Max（tskwd）：	0.2 ns
座面最大高度：	1.727 mm	子类别：	Clock Drivers
最大供电电压 (Vsup)：	3.6 V	最小供电电压 (Vsup)：	3 V
标称供电电压 (Vsup)：	3.3 V	表面贴装：	YES
技术：	CMOS	温度等级：	INDUSTRIAL
端子面层：	TIN LEAD	端子形式：	GULL WING
端子节距：	1.27 mm	端子位置：	DUAL
处于峰值回流温度下的最长时间：	30	宽度：	3.8985 mm
最小 fmax：	133.3 MHz	Base Number Matches：	1

CY2308SI-2T 数据手册

CY2308

3.3V Zero Delay Buffer

Input Decoding” on page 2”. If all output clocks are not

required, Bank B is three-stated. The input clock is directly

applied to the output for chip and system testing purposes by

the select inputs.

Features

■ Zero input-output propagation delay, adjustable by

capacitive load on FBK input

The CY2308 PLL enters a power down state when there are

no rising edges on the REF input. In this mode, all outputs are

three-stated and the PLL is turned off resulting in less than

50 μA of current draw. The PLL shuts down in two additional

cases as shown in the table “Select Input Decoding” on

page 2.

■ Multiple configurations, see “Available CY2308 Configura-

tions” on page 3

■ Multiple low skew outputs

■ Two banks of four outputs, three-stateable by two select

inputs

Multiple CY2308 devices accept the same input clock and

distribute it in a system. In this case, the skew between the

outputs of two devices is less than 700 ps.

■ 10 MHz to 133 MHz operating range

■ 75 ps typical cycle-to-cycle jitter (15 pF, 66 MHz)

■ Spacesaving16-pin 150milSOICpackageor16-pinTSSOP

■ 3.3V operation

The CY2308 is available in five different configurations as

shown in the table “Available CY2308 Configurations” on

page 3. The CY2308–1 is the base part where the output

frequencies equal the reference if there is no counter in the

feedback path. The CY2308–1H is the high drive version of the

–1 and rise and fall times on this device are much faster.

■ Industrial Temperature available

Functional Description

The CY2308–2 enables the user to obtain 2X and 1X

frequencies on each output bank. The exact configuration and

output frequencies depend on the output that drives the

feedback pin. The CY2308–3 enables the user to obtain 4X

and 2X frequencies on the outputs.

The CY2308 is a 3.3V Zero Delay Buffer designed to distribute

high speed clocks in PC, workstation, datacom, telecom, and

other high performance applications.

The part has an on-chip PLL that locks to an input clock

presented on the REF pin. The PLL feedback is driven into the

FBK pin and obtained from one of the outputs. The

input-to-output skew is less than 350 ps and output-to-output

skew is less than 200 ps.

The CY2308–4 enables the user to obtain 2X clocks on all

outputs. Thus, the part is extremely versatile and is used in a

variety of applications.

The CY2308–5H is a high drive version with REF/2 on both

banks.

The CY2308 has two banks of four outputs each that is

controlled by the Select inputs as shown in the table “Select

Logic Block Diagram

FBK

PLL

REF

MUX

CLKA1

CLKA2

CLKA3

CLKA4

Extra Divider (–3, –4)

Extra Divider (–5H)

Select Input

Decoding

CLKB1

CLKB2

CLKB3

CLKB4

Extra Divider (–2, –3)

Cypress Semiconductor Corporation

Document Number: 38-07146 Rev. *E

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised August 03, 2007

[+] Feedback

12 3 4 5 6 7...15

中文翻译

下载PDF

与CY2308SI-2T相关器件

型号	品牌	获取价格	描述	数据表
CY2308SI-2T[19]	CYPRESS	获取价格	3.3 V Zero Delay Buffer
CY2308SI-3	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SI-3	ROCHESTER	获取价格	PLL Based Clock Driver,
CY2308SI-3T	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308SI-3T	ROCHESTER	获取价格	2308 SERIES, PLL BASED CLOCK DRIVER, 8 TRUE OUTPUT(S), 0 INVERTED OUTPUT(S), PDSO16, 0.150
CY2308SI-4	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SI-4T	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SI-5H	CYPRESS	获取价格	3.3V Zero Delay Buffer
CY2308SI-5HT	CYPRESS	获取价格	PLL Based Clock Driver, 2308 Series, 8 True Output(s), 0 Inverted Output(s), CMOS, PDSO16,
CY2308SXC-1	CYPRESS	获取价格	3.3V Zero Delay Buffer

与CY2308SI-2T相关文章

解析光耦仿真器：升级光耦合器技术的必要性
2024-11-18

24
英伟达新一代Blackwell GPU过热问题致交付延迟
2024-11-18

16
国产厂商思特威CMOS图像传感器芯片单月出货超1亿颗，技术创新引领行业发展
2024-11-14

48
台积电5nm和3nm产能利用率达100%，半导体行业景气度持续攀升
2024-11-14

46

产品中心

服务支持

精选活动

关于我们

帮助中心

CY2308SI-2T

CY2308SI-2T 技术参数

CY2308SI-2T 数据手册

与CY2308SI-2T相关器件

与CY2308SI-2T相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CY2308SI-2T

CY2308SI-2T 技术参数

CY2308SI-2T 数据手册

与CY2308SI-2T相关器件

与CY2308SI-2T相关文章

您还可以找

您在本页遇到什么问题？