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CY23020LFI-1T PDF预览

CY23020LFI-1T

更新时间: 2024-01-19 18:52:33
品牌 Logo 应用领域
赛普拉斯 - CYPRESS /
页数 文件大小 规格书
10页 124K
描述
20-output, 200-MHz Zero Delay Buffer

CY23020LFI-1T 技术参数

是否Rohs认证: 不符合生命周期:Obsolete
零件包装代码:QFN包装说明:7 X 7 MM, QFN-48
针数:48Reach Compliance Code:not_compliant
HTS代码:8542.39.00.01风险等级:5.85
其他特性:ALSO OPERATES WITH 3.3V SUPPLY系列:23020
输入调节:STANDARDJESD-30 代码:S-XQCC-N48
JESD-609代码:e0长度:7 mm
逻辑集成电路类型:PLL BASED CLOCK DRIVER功能数量:1
反相输出次数:端子数量:48
实输出次数:20最高工作温度:85 °C
最低工作温度:-40 °C输出特性:3-STATE
封装主体材料:UNSPECIFIED封装代码:VQCCN
封装等效代码:LCC48,.27SQ,20封装形状:SQUARE
封装形式:CHIP CARRIER, VERY THIN PROFILE峰值回流温度(摄氏度):NOT SPECIFIED
电源:2.5/3.3,3.3 V认证状态:Not Qualified
Same Edge Skew-Max(tskwd):0.085 ns座面最大高度:1 mm
子类别:Clock Drivers最大供电电压 (Vsup):2.625 V
最小供电电压 (Vsup):2.375 V标称供电电压 (Vsup):2.5 V
表面贴装:YES温度等级:INDUSTRIAL
端子面层:Tin/Lead (Sn/Pb)端子形式:NO LEAD
端子节距:0.5 mm端子位置:QUAD
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:7 mm
最小 fmax:200 MHzBase Number Matches:1

CY23020LFI-1T 数据手册

 浏览型号CY23020LFI-1T的Datasheet PDF文件第1页浏览型号CY23020LFI-1T的Datasheet PDF文件第2页浏览型号CY23020LFI-1T的Datasheet PDF文件第3页浏览型号CY23020LFI-1T的Datasheet PDF文件第5页浏览型号CY23020LFI-1T的Datasheet PDF文件第6页浏览型号CY23020LFI-1T的Datasheet PDF文件第7页 
CY23020-1  
Vref Source  
C
byp  
C
byp  
50  
50Ω  
FBIN-  
Ref-  
FBIN+  
Ref+  
RS  
R
S
Q19  
Q18  
FBOUT  
Q1  
CL  
CL  
Q17  
Q2  
.
.
.
.
.
.
Q10  
Q9  
Figure 3. Establishing Reference Voltages  
The CY23020-1 uses a differential input receiver to increase  
its rejection of common mode input noise and thus increase  
device performance. To ensure that any noise appears equally  
on both the REFand REF+ pins, it is necessary to match the  
external impedance and circuitry seen at these pins. Figure 3  
shows how this may be accomplished. The reference voltage,  
VREF can be generated by a resistor divider from a power  
supply. This potential will adjust the FBIN+ inputs triggering  
threshold. The reference voltage should be well bypassed so  
as to not introduce any single ended noise to the device. Note  
that the impedance (50 ohms) is also matched to the FBIN+  
line. The 50 ohm resistor is used to create a likeload on the  
REFinput clock signal and matches the 50-ohm source  
impedance of the REF+ input signal. If the input impedance is  
significantly different than 50 ohms, the reference resistor  
should be adjusted accordingly.  
Document #: 38-07120 Rev. *B  
Page 4 of 10  

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