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CY22701FSXI

更新时间： 2024-11-18 04:37:55

品牌	Logo	应用领域
赛普拉斯 - CYPRESS		时钟发生器
页数	文件大小	规格书
15页	140K
描述
1 PLL In-System Programmable Clock Generator

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中文翻译

获取价格

数据手册

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CY22701FSXI 数据手册

PRELIMINARY

CY22701

1 PLL In-System Programmable Clock Generator

Features

Benefits

• In-system programmable through I²C Serial

Programming Interface (SPI)

• Custom timing solutions for designs not suitable for

factory custom silicon, Xtals, or ASICs for production

• Programmable SRAM and non-volatile EEPROM

memory bits with 3.3V supply

• Program and optimize designs while chip is on system

board

• Integrated, phase-locked loop with programmable P

and Q counters, output dividers

• Programming voltages contained in chip

• High-performance PLL enables control of output

frequencies that are customizable to support a wide

range of applications

• Low-jitter, high-accuracy outputs

• 3.3V Operation

• Meets critical timing requirements in complex system

designs

• 8-lead SOIC

• Meets industry-standard voltage platforms

• Industry standard packaging saves on board space

Part Number No. of Outputs

CY22701

Input Frequency Range

Output Frequency Range

1 – 167 MHz (Driven Clock Input) {Commercial} 80 kHz – 200 MHz (3.3V) {Commercial}

1 –150 MHz (Driven Clock Input) {Industrial}

8 – 30 MHz (Crystal Reference) {Comm. or Ind.}

80 kHz –167 MHz (3.3V) {Industrial}

Logic Block Diagram

Output

Crosspoint

Switch

XIN

OUTPUT

DIVIDERS

OSC

CLK1

CLK2

XOUT

Array

VCO

PLL

Clock

Configuration

EEPROM

Memory Array

Pin Configuration

SCL

[I C- SPI:]

SDAT

XOUT

XIN

CLK2/WP

VDD

SDA

VSS

VDD VSS

CLK1

SCL

8 PIN SOIC

Cypress Semiconductor Corporation

Document #: 38-07698 Rev. *B

•

3901 North First Street

•

San Jose

CA 95134

•

408-943-2600

RevisedFebruary8, 2005

12 3 4 5 6 7...15

中文翻译

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