Datasheet > CY15B104Q-LHXI

CY15B104Q-LHXI

更新时间： 2024-04-24 09:03:39

品牌	Logo	应用领域
英飞凌 - INFINEON		存储
页数	文件大小	规格书
22页	828K
描述
铁电存储器 (F-RAM)

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CY15B104Q-LHXI 数据手册

CY15B104Q

For a microcontroller that has no dedicated SPI bus, a

general-purpose port may be used. To reduce hardware

resources on the controller, it is possible to connect the two data

pins (SI, SO) together and tie off (HIGH) the HOLD and WP pins.

Figure 4 shows such a configuration, which uses only three pins.

Serial Opcode

After the slave device is selected with CS going LOW, the first

byte received is treated as the opcode for the intended operation.

CY15B104Q uses the standard opcodes for memory accesses.

Invalid Opcode

Most Significant Bit (MSB)

If an invalid opcode is received, the opcode is ignored and the

device ignores any additional serial data on the SI pin until the

next falling edge of CS, and the SO pin remains tristated.

The SPI protocol requires that the first bit to be transmitted is the

Most Significant Bit (MSB). This is valid for both address and

data transmission.

Status Register

The 4-Mbit serial F-RAM requires a 3-byte address for any read

or write operation. Because the address is only 19 bits, the first

five bits, which are fed in are ignored by the device. Although

these five bits are ‘don’t care’, Cypress recommends that these

bits be set to 0s to enable seamless transition to higher memory

densities.

CY15B104Q has an 8-bit Status Register. The bits in the Status

described in Table 3 on page 7.

Figure 3. System Configuration with SPI Port

SCK

MOSI

MISO

SCK

CY15B104Q

HOLD WP

SCK

CY15B104Q

HOLD WP

SI SO

SPI

Microcontroller

C S 1

H O LD 1

W P 1

C S 2

H O LD 2

W P 2

Figure 4. System Configuration without SPI Port

P1.0

P1.1

SCK

CY15B104Q

HOLD WP

SI SO

Microcontroller

P1.2

The two SPI modes are shown in Figure 5 and Figure 6 on page

6. The status of the clock when the bus master is not transferring

data is:

SPI Modes

CY15B104Q may be driven by a microcontroller with its SPI

peripheral running in either of the following two modes:

■ SCK remains at 0 for Mode 0

■ SCK remains at 1 for Mode 3

■ SPI Mode 0 (CPOL = 0, CPHA = 0)

■ SPI Mode 3 (CPOL = 1, CPHA = 1)

The device detects the SPI mode from the status of the SCK pin

when the device is selected by bringing the CS pin LOW. If the

SCK pin is LOW when the device is selected, SPI Mode 0 is

assumed and if the SCK pin is HIGH, it works in SPI Mode 3.

For both these modes, the input data is latched in on the rising

edge of SCK starting from the first rising edge after CS goes

active. If the clock starts from a HIGH state (in mode 3), the first

rising edge after the clock toggles is considered. The output data

is available on the falling edge of SCK.

Document Number: 001-94240 Rev. *E

Page 5 of 22

1 2 3 456 7 8...22

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与CY15B104Q-LHXI相关器件

型号	品牌	描述	获取价格	数据表
CY15B104Q-LHXIT	CYPRESS	Memory Circuit, 512KX8, CMOS, PDSO8, TDFN-8	获取价格
CY15B104Q-LHXIT	INFINEON	铁电存储器 (F-RAM)	获取价格
CY15B104QN-20LPXC	INFINEON	4Mb 3.3V Commercial 20MHz SPI EXCELON? F-RAM in 8-pin GQFN	获取价格
CY15B104QN-20LPXCT	INFINEON	4Mb 3.3V Commercial 20MHz SPI EXCELON? F-RAM in 8-pin GQFN	获取价格
CY15B104QN-20LPXI	INFINEON	4Mb 3.3V Industrial 20MHz SPI EXCELON? F-RAM in 8-pin GQFN	获取价格
CY15B104QN-20LPXIT	INFINEON	4Mb 3.3V Industrial 20MHz SPI EXCELON? F-RAM in 8-pin GQFN	获取价格

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