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CY14B104L-BA15XI PDF预览

CY14B104L-BA15XI

更新时间: 2024-02-27 13:58:21
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 存储内存集成电路静态存储器
页数 文件大小 规格书
22页 663K
描述
4-Mbit (512K x 8/256K x 16) nvSRAM

CY14B104L-BA15XI 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:BGA包装说明:TFBGA, BGA48,6X8,30
针数:48Reach Compliance Code:compliant
ECCN代码:3A991.B.2.AHTS代码:8542.32.00.41
风险等级:5.67最长访问时间:15 ns
JESD-30 代码:R-PBGA-B48长度:10 mm
内存密度:4194304 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8混合内存类型:N/A
功能数量:1端子数量:48
字数:524288 words字数代码:512000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:512KX8
封装主体材料:PLASTIC/EPOXY封装代码:TFBGA
封装等效代码:BGA48,6X8,30封装形状:RECTANGULAR
封装形式:GRID ARRAY, THIN PROFILE, FINE PITCH并行/串行:PARALLEL
峰值回流温度(摄氏度):260电源:3/3.3 V
认证状态:Not Qualified座面最大高度:1.2 mm
最大待机电流:0.003 A子类别:SRAMs
最大压摆率:0.075 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子形式:BALL
端子节距:0.75 mm端子位置:BOTTOM
处于峰值回流温度下的最长时间:NOT SPECIFIED宽度:6 mm
Base Number Matches:1

CY14B104L-BA15XI 数据手册

 浏览型号CY14B104L-BA15XI的Datasheet PDF文件第2页浏览型号CY14B104L-BA15XI的Datasheet PDF文件第3页浏览型号CY14B104L-BA15XI的Datasheet PDF文件第4页浏览型号CY14B104L-BA15XI的Datasheet PDF文件第5页浏览型号CY14B104L-BA15XI的Datasheet PDF文件第6页浏览型号CY14B104L-BA15XI的Datasheet PDF文件第7页 
PRELIMINARY  
CY14B104L, CY14B104N  
4-Mbit (512K x 8/256K x 16) nvSRAM  
Features  
Functional Description  
15 ns, 25 ns, and 45 ns access times  
The Cypress CY14B104L/CY14B104N is a fast static RAM, with  
a nonvolatile element in each memory cell. The memory is  
Internally organized as 512K x 8 (CY14B104L) or 256K x 16  
(CY14B104N)  
organized as 512K words of 8 bits each or 256K words of 16 bits  
each. The embedded nonvolatile elements incorporate  
QuantumTrap technology, producing the world’s most reliable  
nonvolatile memory. The SRAM provides infinite read and write  
cycles, while independent nonvolatile data resides in the highly  
reliable QuantumTrap cell. Data transfers from the SRAM to the  
nonvolatile elements (the STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM (the RECALL operation) from the nonvolatile memory.  
Both the STORE and RECALL operations are also available  
under software control.  
Hands off automatic STORE on power down with only a small  
capacitor  
STORE to QuantumTrap® nonvolatile elements initiated by  
software, device pin or AutoStore® on power down  
RECALL to SRAM initiated by software or power up  
Infinite read, write, and recall cycles  
8 mA typical ICC at 200 ns cycle time  
200,000 STORE cycles to QuantumTrap  
20 year data retention  
Single 3V +20%, –10% operation  
Commercial and industrial temperatures  
FBGA and TSOP - II packages  
RoHS compliance  
Logic Block Diagram  
VCC  
VCAP  
[1]  
A0 - A18  
Address  
[1]  
DQ0 - DQ7  
CE  
OE  
WE  
CY14B104L  
CY14B104N  
HSB  
BHE  
BLE  
VSS  
Note  
1. Address A - A and Data DQ0 - DQ7 for x8 configuration, Address A - A and Data DQ0 - DQ15 for x16 configuration.  
0
18  
0
17  
Cypress Semiconductor Corporation  
Document #: 001-07102 Rev. *F  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 02, 2008  
[+] Feedback  

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