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CY14B101K-SP35XCT PDF预览

CY14B101K-SP35XCT

更新时间: 2024-01-30 09:09:10
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器时钟
页数 文件大小 规格书
24页 1357K
描述
1 Mbit (128K x 8) nvSRAM With Real-Time Clock

CY14B101K-SP35XCT 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Active零件包装代码:SSOP
包装说明:SSOP,针数:48
Reach Compliance Code:unknown风险等级:5.66
最长访问时间:35 nsJESD-30 代码:R-PDSO-G48
JESD-609代码:e3长度:15.875 mm
内存密度:1048576 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:48
字数:131072 words字数代码:128000
工作模式:ASYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:SSOP
封装形状:RECTANGULAR封装形式:SMALL OUTLINE, SHRINK PITCH
并行/串行:PARALLEL峰值回流温度(摄氏度):260
认证状态:COMMERCIAL座面最大高度:2.794 mm
最大供电电压 (Vsup):3.6 V最小供电电压 (Vsup):2.7 V
标称供电电压 (Vsup):3 V表面贴装:YES
技术:CMOS温度等级:INDUSTRIAL
端子面层:MATTE TIN端子形式:GULL WING
端子节距:0.635 mm端子位置:DUAL
处于峰值回流温度下的最长时间:20宽度:7.505 mm
Base Number Matches:1

CY14B101K-SP35XCT 数据手册

 浏览型号CY14B101K-SP35XCT的Datasheet PDF文件第2页浏览型号CY14B101K-SP35XCT的Datasheet PDF文件第3页浏览型号CY14B101K-SP35XCT的Datasheet PDF文件第4页浏览型号CY14B101K-SP35XCT的Datasheet PDF文件第5页浏览型号CY14B101K-SP35XCT的Datasheet PDF文件第6页浏览型号CY14B101K-SP35XCT的Datasheet PDF文件第7页 
PRELIMINARY  
CY14B101K  
1 Mbit (128K x 8) nvSRAM With Real-Time Clock  
Features  
Functional Description  
• Data integrity of Cypress nvSRAM combined with full  
featured Real-Time Clock (RTC)  
The Cypress CY14B101K combines a 1 Mbit nonvolatile static  
RAM with a full featured real-time clock in a monolithic  
integrated circuit. The embedded nonvolatile elements  
incorporate QuantumTrap technology producing the world’s  
most reliable nonvolatile memory. The SRAM can be read and  
written an infinite number of times, while independent,  
nonvolatile data resides in the nonvolatile elements.  
• Watchdog timer  
• Clock alarm with programmable interrupts  
• Capacitor or battery backup for RTC  
• 25 ns, 35 ns, and 45 ns access times  
The Real-Time Clock function provides an accurate clock with  
leap year tracking and a programmable, high accuracy  
oscillator. The alarm function is programmable for one time  
alarm or periodic seconds, minutes, hours, or days. There is  
also a programmable watchdog timer for process control.  
• “Hands-off” automatic STORE on power down with only a  
small capacitor  
STOREtoQuantumTrapinitiatedbysoftware, devicepin,  
or on power down  
RECALL to SRAM initiated by software or on power up  
• Infinite READ, WRITE, and RECALL cycles  
• High reliability  
— Endurance to 200,000 cycles  
Data retention: 20 years @55°C  
• 10 mA typical ICC at 200 ns cycle time  
• Single 3V operation +20%, –10%  
• Commercial and industrial temperature  
• SSOP package (ROHS compliant)  
Logic Block Diagram  
V
CC  
V
CAP  
QuantumTrap  
1024 x 1024  
V
RTCbat  
A5  
A6  
A7  
A8  
POWER  
CONTROL  
STORE  
RECALL  
V
RTCcap  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
1024 X 1024  
A9  
HSB  
A12  
A13  
A14  
A15  
A16  
SOFTWARE  
DETECT  
A15  
-A0  
DQ0  
COLUMN IO  
DQ1  
DQ2  
DQ3  
DQ4  
DQ5  
DQ6  
DQ7  
COLUMN DEC  
x1  
x2  
INT  
RTC  
MUX  
A0  
A4  
A11  
A10  
A1  
A3  
A2  
A16  
-A0  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document #: 001-06401 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised March 01, 2007  
[+] Feedback  

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