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CY14B101L PDF预览

CY14B101L

更新时间: 2024-02-13 17:04:36
品牌 Logo 应用领域
赛普拉斯 - CYPRESS 静态存储器
页数 文件大小 规格书
18页 1205K
描述
1-Mbit (128K x 8) nvSRAM

CY14B101L 技术参数

是否Rohs认证: 符合生命周期:Obsolete
零件包装代码:SOIC包装说明:SOP, SOP16,.4
针数:16Reach Compliance Code:compliant
ECCN代码:EAR99HTS代码:8542.32.00.41
风险等级:5.42JESD-30 代码:R-PDSO-G16
JESD-609代码:e4长度:10.2865 mm
内存密度:1048576 bit内存集成电路类型:NON-VOLATILE SRAM
内存宽度:8湿度敏感等级:3
功能数量:1端子数量:16
字数:131072 words字数代码:128000
工作模式:SYNCHRONOUS最高工作温度:85 °C
最低工作温度:-40 °C组织:128KX8
封装主体材料:PLASTIC/EPOXY封装代码:SOP
封装等效代码:SOP16,.4封装形状:RECTANGULAR
封装形式:SMALL OUTLINE并行/串行:SERIAL
峰值回流温度(摄氏度):260电源:3/3.3 V
认证状态:Not Qualified座面最大高度:2.667 mm
最大待机电流:0.005 A子类别:SRAMs
最大压摆率:0.01 mA最大供电电压 (Vsup):3.6 V
最小供电电压 (Vsup):2.7 V标称供电电压 (Vsup):3 V
表面贴装:YES技术:CMOS
温度等级:INDUSTRIAL端子面层:Nickel/Palladium/Gold (Ni/Pd/Au)
端子形式:GULL WING端子节距:1.27 mm
端子位置:DUAL处于峰值回流温度下的最长时间:40
宽度:7.4925 mmBase Number Matches:1

CY14B101L 数据手册

 浏览型号CY14B101L的Datasheet PDF文件第2页浏览型号CY14B101L的Datasheet PDF文件第3页浏览型号CY14B101L的Datasheet PDF文件第4页浏览型号CY14B101L的Datasheet PDF文件第5页浏览型号CY14B101L的Datasheet PDF文件第6页浏览型号CY14B101L的Datasheet PDF文件第7页 
PRELIMINARY  
CY14B101L  
1-Mbit (128K x 8) nvSRAM  
Features  
Functional Description  
• 25 ns, 35 ns, and 45 ns access times  
The Cypress CY14B101L is a fast static RAM with a  
nonvolatile element in each memory cell. The embedded  
nonvolatile elements incorporate QuantumTrap technology  
producing, the world’s most reliable nonvolatile memory. The  
SRAM provides infinite read and write cycles; while  
independent, nonvolatile data resides in the highly reliable  
QuantumTrap cell. Data transfers from the SRAM to the  
nonvolatile elements (the STORE operation) takes place  
automatically at power down. On power up, data is restored to  
the SRAM (the RECALL operation) from the nonvolatile  
memory. Both the STORE and RECALL operations are also  
available under software control.  
• “Hands-off” automatic STORE on power down with only a  
small capacitor  
STOREto QuantumTrapTM nonvolatile elements is initiated  
by software, device pin, or AutostoreTM on power down  
RECALL to SRAM initiated by software or power up  
• Infinite READ, WRITE, and RECALL cycles  
• 10 mA typical ICC at 200 ns cycle time  
• 200,000 STORE cycles to quantum trap  
20-year data retention @ 55°C  
Single 3V operation +20%, –10%  
• Commercial and industrial temperature  
• SOIC and SSOP packages  
• RoHS compliance  
Logic Block Diagram  
V
CC  
V
CAP  
QuantumTrap  
1024 x 1024  
A5  
POWER  
STORE  
RECALL  
CONTROL  
A6  
A7  
A8  
STORE/  
RECALL  
CONTROL  
STATIC RAM  
ARRAY  
1024 X 1024  
A9  
HSB  
A12  
A13  
A14  
A15  
A16  
SOFTWARE  
DETECT  
A15  
-
A0  
DQ0  
COLUMN IO  
DQ1  
DQ2  
DQ3  
COLUMN DEC  
DQ4  
DQ5  
DQ6  
DQ7  
A0  
A4  
A11  
A10  
A1  
A3  
A2  
OE  
CE  
WE  
Cypress Semiconductor Corporation  
Document #: 001-06400 Rev. *E  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised January 24, 2007  
[+] Feedback  

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