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CXD2720Q-2 PDF预览

CXD2720Q-2

更新时间: 2024-10-27 22:08:07
品牌 Logo 应用领域
索尼 - SONY 解码器消费电路商用集成电路ISM频段
页数 文件大小 规格书
47页 530K
描述
Single-Chip Dolby Pro Logic Surround Decoder

CXD2720Q-2 技术参数

是否无铅: 不含铅是否Rohs认证: 符合
生命周期:Obsolete零件包装代码:QFP
包装说明:QFP, QFP100,.7X.9针数:100
Reach Compliance Code:unknownHTS代码:8542.39.00.01
风险等级:5.83Is Samacsys:N
商用集成电路类型:CONSUMER CIRCUITJESD-30 代码:R-PQFP-G100
JESD-609代码:e6/e4长度:20 mm
功能数量:1端子数量:100
最高工作温度:75 °C最低工作温度:-20 °C
封装主体材料:PLASTIC/EPOXY封装代码:QFP
封装等效代码:QFP100,.7X.9封装形状:RECTANGULAR
封装形式:FLATPACK峰值回流温度(摄氏度):260
电源:5 V认证状态:Not Qualified
座面最大高度:3.1 mm子类别:Other Consumer ICs
最大压摆率:90 mA最大供电电压 (Vsup):5.5 V
最小供电电压 (Vsup):4.5 V表面贴装:YES
技术:CMOS温度等级:COMMERCIAL EXTENDED
端子面层:TIN BISMUTH/PALLADIUM端子形式:GULL WING
端子节距:0.65 mm端子位置:QUAD
处于峰值回流温度下的最长时间:10宽度:14 mm
Base Number Matches:1

CXD2720Q-2 数据手册

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CXD2720Q-2  
Pin Description  
Pin  
Symbol  
No.  
I/O  
Description  
1
2
3
4
5
AVS0  
VSS0  
RVDT  
SCK  
I
DRAM digital GND.  
Digital GND.  
Data input for microcomputer interface.  
Shift clock input for microcomputer interface.  
Latch input for microcomputer interface.  
I
XLAT  
I
Transmission enabling signal output for microcomputer interface. Transmission  
prohibited when Low.  
6
REDY  
O
7
TRDT  
XWO  
XRST  
VSS1  
VDD0  
SO  
O
I
Serial data output for microcomputer interface.  
Window open input for synchronization. Normally High.  
System reset input. Resets when Low.  
Digital GND.  
8
9
I
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
25  
26  
27  
28  
29  
30  
31  
32  
33  
34  
35  
O
I
Digital power supply.  
1-sampling 2-channel serial data output.  
Serial data 24-/32-bit slot selection. 24-bit slot when Low. (valid for slave mode)  
Test pin. Normally set Low.  
XS24  
TST0  
TST1  
TST2  
TST3  
TST4  
TST5  
VSS2  
AVS3  
AIN3  
AVD3  
AVD4  
AO1P  
AO1N  
AVS4  
AVS1  
AIN1  
AVD1  
XVDD  
XTLO  
XTLI  
I
I
Test pin. Normally set Low.  
I
Test pin. Normally set Low.  
I
Test pin. Normally set Low.  
I
Test pin. Normally set Low.  
I
Test pin. Normally set Low.  
I
Digital GND.  
CH3 AD converter GND.  
CH3 AD converter analog input (for microphone input).  
CH3 AD converter power supply.  
CH1 DA converter power supply.  
CH1 DA converter analog positive phase output.  
CH1 DA converter analog reversed phase output.  
CH1 DA converter GND.  
O
O
I
CH1 AD converter GND.  
CH1 AD converter analog input.  
CH1 AD converter power supply.  
Digital power supply for master clock.  
Crystal oscillator circuit output.  
O
I
Crystal oscillator circuit input.  
XVSS  
AVS2  
Digital GND for master clock.  
CH2 AD converter GND.  
– 3 –  

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