Datasheet > CPLL-018M-200.00

CPLL-018M-200.00

更新时间： 2024-11-05 03:26:31

品牌	Logo	应用领域
CRYSTEKMICROWAVE		振荡器时钟
页数	文件大小	规格书
1页	117K
描述
Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS

阅读下载

中文翻译

获取价格

数据手册

如果您发现信息不准确，欢迎纠错

CPLL-018M-200.00 数据手册

Programmable

Clock Oscillator

PLL Based Design

CPLL-018 Model

5X7 mm SMD, 3.3V, CMOS

Frequency Range:

1.544MHz to 200MHz

Frequency Stability:

Temperature Range:

Operating:

±25ppm, ±50ppm, ±100ppm

0°C to 70°C

(Option M) -20°C to 70°C

(Option X)

Storage:

-40°C to 85°C

Designed to meet today's

requirements for economical

3.3V applications. Available

on 16mm tape and reel in

quantities of 1K.

-55°C to 120°C

3.3V ± 0.3V

Input Voltage:

Input Current:

Output:

45mA Max

CMOS

Symmetry:

40/60% Max @ 50% Vdd

10ns Max @ 20/% to 80% Vdd

"0" = 80% Vdd Max

"1" = 90% Vdd Min

15pF

Rise/Fall Time:

Logic:

Load:

Jitter:

150pS pk-pk Max

Aging:

<3ppm 1st/yr, <1ppm every year hereafter

SUGGESTED PAD LAYOUT

Dimensions inches (mm)

0.055 Typ

(1.40 Typ)

All dimensions are Max unless otherwise specified.

0.071 SQ

(1.80)

0.295 Max

(7.50)

0.165

(4.19)

0.045 ±0.008

(1.14 ±0.20)

P/N

0.204 Max

0.075 Max #4

(1.80)

(5.02)

Freq DC

0.200

(5.08)

Denotes pad 1

0.200 ±0.005

(5.08 ±0.13)

0.01uF Bypass Capacitor Recommended

RECOMMENDED REFLOW SOLDERING PROFILE

Ramp-Up

Critical Temperature

3°C/Sec Max.

Crystek Part Number Guide

CPLL-018 X- 25 - 200.000

Zone

Ramp-Down

6°C/Sec.

260°C

217°C

200°C

Stability Indicator

#1 Crystek Clock PLL Osc.

#2 Model

150°C

Blank (std)

± 100ppm

#3 Temp. Range: Blank= 0/70°C, M= -20/70°C, X= -40/85°C

#4 Stability: (see Table 1)

25ppm

50ppm

#5 Frequency in MHz: 3 or 6 decimal places

Preheat

90 Secs. Max.

180 Secs. Max.

Table 1

Example:

8 Minutes Max.

CPLL-018X-25-200.000

CPLL-018-50-19.660800

3.3V Tristate, -40/85°C, 25ppm, 200.000 MHz

3.3V Tristate, 0/70, 50ppm, 19.660800 MHz

260°C for

10 Secs. Max.

NOTE: Reflow Profile with 240°C peak also acceptable.

OUT

Tri-State Function

pin 3

pin 4

Function pin 1

Output pin

O/P Load

Vdd

OUT

incl Probe Cl

Open

"1" level 2.4V Min

"0" level 0.4V Max

Active

High Z

PWR

OSC.

Bypass

Cap.

Supply

GND

pin 1

pin 2

High Impedance

GND or "LOW"

Oscillation

OPEN or "HIGH"

TD-040405 Rev.C

Specifications subject to change without notice.

中文翻译

下载PDF

与CPLL-018M-200.00相关器件

型号	品牌	获取价格	描述	数据表
CPLL-018M-25-200.00	CRYSTEKMICROWAVE	获取价格	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS
CPLL-018M-50-200.00	CRYSTEKMICROWAVE	获取价格	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS
CPLL-018X-200.00	CRYSTEKMICROWAVE	获取价格	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS
CPLL-018X-25-200.00	CRYSTEKMICROWAVE	获取价格	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS
CPLL-018X-50-200.00	CRYSTEKMICROWAVE	获取价格	Programmable Clock Oscillator PLL Based Design 5X7 mm SMD, 3.3V, CMOS
CPLL58-1600-2200	CRYSTEKMICROWAVE	获取价格	RF PLL Synthensizer
CPLL58-2175-2175	CRYSTEKMICROWAVE	获取价格	RF PLL Synthesizer
CPLL58-2400-2500	CRYSTEKMICROWAVE	获取价格	RF PLL Synthesizer
CPLL58-2416-2553	CRYSTEKMICROWAVE	获取价格	RF PLL Synthesizer
CPLL58-2450-2450	CRYSTEKMICROWAVE	获取价格	RF PLL Synthesizer

与CPLL-018M-200.00相关文章

英伟达新AI芯片Rubin或提前半年亮相
2024-11-05

13
苹果iPhone 17将全系采用三星/LG显示LTPO OLED面板
2024-11-05

9
三星深化印度制造布局，供应链本地化进程加速
2024-10-29

35
芯擎科技“星辰一号”自动驾驶芯片点亮成功，2025年量产在即
2024-10-29

31

产品中心

服务支持

精选活动

关于我们

帮助中心

CPLL-018M-200.00

CPLL-018M-200.00 数据手册

与CPLL-018M-200.00相关器件

与CPLL-018M-200.00相关文章

您还可以找

产品中心

服务支持

精选活动

关于我们

帮助中心

CPLL-018M-200.00

CPLL-018M-200.00 数据手册

与CPLL-018M-200.00相关器件

与CPLL-018M-200.00相关文章

您还可以找

您在本页遇到什么问题？