Programmable
Clock Oscillator
PLL Based Design
CPLL-018 Model
5X7 mm SMD, 3.3V, CMOS
Frequency Range:
1.544MHz to 200MHz
Frequency Stability:
Temperature Range:
Operating:
±25ppm, ±50ppm, ±100ppm
0°C to 70°C
(Option M) -20°C to 70°C
(Option X)
Storage:
-40°C to 85°C
Designed to meet today's
requirements for economical
3.3V applications. Available
on 16mm tape and reel in
quantities of 1K.
-55°C to 120°C
3.3V ± 0.3V
Input Voltage:
Input Current:
Output:
45mA Max
CMOS
Symmetry:
40/60% Max @ 50% Vdd
10ns Max @ 20/% to 80% Vdd
"0" = 80% Vdd Max
"1" = 90% Vdd Min
15pF
Rise/Fall Time:
Logic:
Load:
Jitter:
150pS pk-pk Max
Aging:
<3ppm 1st/yr, <1ppm every year hereafter
SUGGESTED PAD LAYOUT
Dimensions inches (mm)
0.055 Typ
(1.40 Typ)
All dimensions are Max unless otherwise specified.
0.071 SQ
(1.80)
0.295 Max
(7.50)
#1
#2
#3
0.165
(4.19)
0.045 ±0.008
(1.14 ±0.20)
P/N
0.204 Max
0.075 Max #4
(1.80)
(5.02)
Freq DC
0.200
(5.08)
Denotes pad 1
0.200 ±0.005
(5.08 ±0.13)
0.01uF Bypass Capacitor Recommended
RECOMMENDED REFLOW SOLDERING PROFILE
Ramp-Up
Critical Temperature
3°C/Sec Max.
Crystek Part Number Guide
CPLL-018 X- 25 - 200.000
Zone
Ramp-Down
6°C/Sec.
260°C
217°C
#1
#2
#3
#4
#5
200°C
Stability Indicator
#1 Crystek Clock PLL Osc.
#2 Model
150°C
Blank (std)
± 100ppm
#3 Temp. Range: Blank= 0/70°C, M= -20/70°C, X= -40/85°C
#4 Stability: (see Table 1)
25
50
±
±
25ppm
50ppm
#5 Frequency in MHz: 3 or 6 decimal places
Preheat
90 Secs. Max.
180 Secs. Max.
Table 1
Example:
8 Minutes Max.
CPLL-018X-25-200.000
CPLL-018-50-19.660800
=
3.3V Tristate, -40/85°C, 25ppm, 200.000 MHz
3.3V Tristate, 0/70, 50ppm, 19.660800 MHz
260°C for
=
10 Secs. Max.
NOTE: Reflow Profile with 240°C peak also acceptable.
OUT
Tri-State Function
mA
M
pin 3
pin 4
Function pin 1
Output pin
O/P Load
Vdd
OUT
incl Probe Cl
Open
"1" level 2.4V Min
"0" level 0.4V Max
Active
Active
High Z
PWR
OSC.
Bypass
Cap.
VM
Supply
GND
pin 1
pin 2
High Impedance
GND or "LOW"
Oscillation
OPEN or "HIGH"
TD-040405 Rev.C
Specifications subject to change without notice.