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CMLDM7003TEGTR PDF预览

CMLDM7003TEGTR

更新时间: 2024-11-24 08:33:51
品牌 Logo 应用领域
CENTRAL /
页数 文件大小 规格书
2页 113K
描述
Power Field-Effect Transistor, N-Channel, Metal-oxide Semiconductor FET

CMLDM7003TEGTR 数据手册

 浏览型号CMLDM7003TEGTR的Datasheet PDF文件第2页 
TM  
CMLDM7003TEG  
Central  
Semiconductor Corp.  
ENHANCED SPECIFICATION  
TM  
SURFACE MOUNT PICOmini  
DESCRIPTION:  
DUAL N-CHANNEL  
SILICON MOSFET  
The CENTRAL SEMICONDUCTOR CMLDM7003TEG  
is an Enhancement-mode N-Channel Field Effect  
Transistor, manufactured by the N-Channel DMOS  
Process, designed for high speed pulsed amplifier and  
driver applications. These special Dual Transistor devices  
offer low drain-source on state resistance (r  
) and  
DS(ON)  
ESD protection up to 2kV, and a Gate-Source Threshold  
Voltage (V ) of 0.75V MIN to 1.0V MAX.  
GS(th)  
MARKING CODE: TEG  
SOT-563 CASE  
FEATURES:  
ENHANCED SPECIFICATION: V  
= 1.0V MAX  
GS(th)  
ESD protection up to 2kV  
Device is Halogen Free by design  
MAXIMUM RATINGS: (T =25°C)  
SYMBOL  
UNITS  
V
A
Drain-Source Voltage  
V
50  
50  
DS  
DG  
GS  
Drain-Gate Voltage  
V
V
V
Gate-Source Voltage  
12  
V
Continuous Drain Current  
Maximum Pulsed Drain Current  
Power Dissipation (Note 1)  
Power Dissipation (Note 2)  
Power Dissipation (Note 3)  
Operating and Storage Junction Temperature  
Thermal Resistance  
I
280  
mA  
A
D
I
1.5  
DM  
P
P
P
350  
mW  
mW  
mW  
°C  
D
D
D
300  
150  
T , T  
-65 to +150  
357  
J
stg  
Θ
°C/W  
JA  
ELECTRICAL CHARACTERISTICS PER TRANSISTOR: (T =25°C unless otherwise noted)  
A
SYMBOL  
TEST CONDITIONS  
MIN  
TYP  
MAX  
UNITS  
nA  
I
I
I
I
I
V
V
V
V
=5V  
50  
GSSF, GSSR  
GS  
GS  
GS  
DS  
I
=10V  
=12V  
0.5  
1.0  
50  
μA  
GSSF, GSSR  
I
μA  
GSSF, GSSR  
=50V, V =0V  
GS  
nA  
DSS  
Notes: (1) Ceramic or aluminum core PC Board with copper mounting pad area of 4.0 mm2  
(2) FR-4 Epoxy PC Board with copper mounting pad area of 4.0 mm2  
(3) FR-4 Epoxy PC Board with copper mounting pad area of 1.4 mm2  
R0 (3-June 2008)  

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