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CLVTH16373MGQLREP PDF预览

CLVTH16373MGQLREP

更新时间： 2024-11-18 02:58:51
品牌 Logo 应用领域
德州仪器 - TI 驱动信息通信管理逻辑集成电路
页数 文件大小 规格书
12页 462K
描述
SN74LVTH16373-EP 3.3-V ABT 16-Bit Transparent D-Type Latch With Tri-State Outputs

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中文翻译

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CLVTH16373MGQLREP 技术参数

生命周期：Lifetime Buy包装说明：VFBGA,
Reach Compliance Code：not_compliantECCN代码：EAR99
Factory Lead Time：1 week风险等级：7.7
系列：LVTJESD-30 代码：R-PBGA-B56
JESD-609代码：e0长度：7 mm
逻辑集成电路类型：BUS DRIVER最大I（ol）：0.064 A
湿度敏感等级：1位数：8
功能数量：2端口数量：2
端子数量：56最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：VFBGA封装形状：RECTANGULAR
封装形式：GRID ARRAY, VERY THIN PROFILE, FINE PITCH传播延迟（tpd）：5.9 ns
座面最大高度：1 mm最大供电电压 (Vsup)：3.6 V
最小供电电压 (Vsup)：2.7 V标称供电电压 (Vsup)：3.3 V
表面贴装：YES技术：BICMOS
温度等级：MILITARY端子面层：Tin/Lead (Sn/Pb)
端子形式：BALL端子节距：0.65 mm
端子位置：BOTTOM宽度：4.5 mm
Base Number Matches：1

CLVTH16373MGQLREP 数据手册

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SCBS778A − NOVEMBER 2003 − REVISED MARCH 2004  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Enhanced Product-Change Notification  
†
Qualification Pedigree  
Member of the Texas Instruments  
WidebusFamily  
DGG OR DL PACKAGE  
(TOP VIEW)  
D
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1
48  
47  
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25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
1LE  
1D1  
1D2  
GND  
1D3  
1D4  
2
3
4
D
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
5
6
3.3-V V  
)
CC  
7
V
V
CC  
CC  
D
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
8
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
9
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
V
V
CC  
CC  
†
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
2D5  
2D6  
GND  
2D7  
2D8  
2LE  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
description/ordering information  
The SN74LVTH16373 is a 16-bit transparent D-type latch with 3-state outputs designed for low-voltage (3.3-V)  
operation, but with the capability to provide a TTL interface to a 5-V system environment. This device is  
V
CC  
particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers.  
This device can be used as two 8-bit latches or one 16-bit latch. When the latch-enable (LE) input is high, the  
Q outputs follow the data (D) inputs. When LE is taken low, the Q outputs are latched at the levels set up at the  
D inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...12

中文翻译

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