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CLVTH16374IDLREP

更新时间： 2024-02-01 16:06:25
品牌 Logo 应用领域
德州仪器 - TI 触发器输出元件
页数 文件大小 规格书
10页 301K
描述
3.3-V ABT 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP WITH 3-STATE OUTPUTS

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CLVTH16374IDLREP 数据手册

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SCBS779A − NOVEMBER 2003 – OCTOBER 2004  
D
D
D
D
D
Controlled Baseline  
− One Assembly/Test Site, One Fabrication  
Site  
D
D
D
Flow-Through Architecture Optimizes PCB  
Layout  
Latch-Up Performance Exceeds 500 mA Per  
JESD 17  
Enhanced Diminishing Manufacturing  
Sources (DMS) Support  
ESD Protection Exceeds JESD 22  
− 2000-V Human-Body Model (A114-A)  
− 200-V Machine Model (A115-A)  
Enhanced Product-Change Notification  
†
Qualification Pedigree  
Member of the Texas Instruments  
WidebusFamily  
DGG OR DL PACKAGE  
(TOP VIEW)  
D
State-of-the-Art Advanced BiCMOS  
Technology (ABT) Design for 3.3-V  
Operation and Low Static-Power  
Dissipation  
1CLK  
1D1  
1D2  
GND  
1D3  
1D4  
1
48  
47  
46  
45  
44  
43  
42  
41  
40  
39  
38  
37  
36  
35  
34  
33  
32  
31  
30  
29  
28  
27  
26  
25  
1OE  
1Q1  
1Q2  
GND  
1Q3  
1Q4  
2
3
4
D
Supports Mixed-Mode Signal Operation  
(5-V Input and Output Voltages With  
5
6
3.3-V V  
)
CC  
7
V
V
CC  
CC  
D
D
D
D
Supports Unregulated Battery Operation  
Down to 2.7 V  
8
1D5  
1D6  
GND  
1D7  
1D8  
2D1  
2D2  
GND  
2D3  
2D4  
1Q5  
1Q6  
GND  
1Q7  
1Q8  
2Q1  
2Q2  
GND  
2Q3  
2Q4  
9
Typical V  
<0.8 V at V  
(Output Ground Bounce)  
OLP  
CC  
10  
11  
12  
13  
14  
15  
16  
17  
18  
19  
20  
21  
22  
23  
24  
= 3.3 V, T = 25°C  
A
I
and Power-Up 3-State Support Hot  
off  
Insertion  
Bus Hold on Data Inputs Eliminates the  
Need for External Pullup/Pulldown  
Resistors  
D
Distributed V  
High-Speed Switching Noise  
and GND Pins Minimize  
CC  
V
V
CC  
CC  
2D5  
2D6  
GND  
2D7  
2D8  
2CLK  
†
2Q5  
2Q6  
GND  
2Q7  
2Q8  
2OE  
Component qualification in accordance with JEDEC and industry  
standards to ensure reliable operation over an extended  
temperature range. This includes, but is not limited to, Highly  
Accelerated Stress Test (HAST) or biased 85/85, temperature  
cycle, autoclave or unbiased HAST, electromigration, bond  
intermetallic life, and mold compound life. Such qualification  
testing should not be viewed as justifying use of this component  
beyond specified performance and environmental limits.  
description/ordering information  
The SN74LVTH16374 is a 16-bit edge-triggered D-type flip-flop with 3-state outputs designed for low-voltage  
(3.3-V) V operation, but with the capability to provide a TTL interface to a 5-V system environment. This  
CC  
device is particularly suitable for implementing buffer registers, I/O ports, bidirectional bus drivers, and working  
registers.  
This device can be used as two 8-bit flip-flops or one 16-bit flip-flop. On the positive transition of the clock (CLK),  
the Q outputs of the flip-flop take on the logic levels set up at the data (D) inputs.  
Please be aware that an important notice concerning availability, standard warranty, and use in critical applications of  
Texas Instruments semiconductor products and disclaimers thereto appears at the end of this data sheet.  
Widebus is a trademark of Texas Instruments.  
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Copyright 2004, Texas Instruments Incorporated  
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ꢢ ꢦ ꢣ ꢢꢛ ꢜꢯ ꢞꢝ ꢡ ꢩꢩ ꢧꢡ ꢟ ꢡ ꢠ ꢦ ꢢ ꢦ ꢟ ꢣ ꢎ  
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1
POST OFFICE BOX 655303 • DALLAS, TEXAS 75265  
1234567...10

中文翻译

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