CL-PS7500FE
System-on-a-Chip for Internet Appliance
6. ARM PROCESSOR MMU .................................................................................................... 38
6.1
MMU Program-Accessible Registers................................................................................................38
6.1.1
6.1.2
6.1.3
6.1.4
Translation Table Base Register ......................................................................................39
Domain Access Control Register......................................................................................39
Fault Status Register ........................................................................................................39
Fault Address Register .....................................................................................................39
6.2
6.3
Address Translation ..........................................................................................................................39
Translation Process ..........................................................................................................................40
6.3.1
6.3.2
6.3.3
6.3.4
6.3.5
TTB (Translation Table Base)............................................................................................40
Level One Fetch................................................................................................................40
Level One Descriptor........................................................................................................41
Page Table Descriptor.......................................................................................................41
Section Descriptor ............................................................................................................42
6.4
Translating Section References........................................................................................................42
6.4.1 Level Two Descriptor.........................................................................................................42
6.5
6.6
6.7
6.8
6.9
6.10
Translating Small Page References..................................................................................................44
Translating Large Page References .................................................................................................45
MMU Faults and CPU Aborts ...........................................................................................................47
Fault Address and Fault Status Registers (FAR, FSR).....................................................................47
Domain Access Control....................................................................................................................48
Fault-Checking Sequence ................................................................................................................48
6.10.1
6.10.2
6.10.3
6.10.4
Alignment Fault.................................................................................................................49
Translation Fault................................................................................................................50
Domain Fault ....................................................................................................................50
Permission Fault ...............................................................................................................50
6.11
External Aborts.................................................................................................................................50
6.11.1 Interaction of the MMU, IDC, and Write Buffer..................................................................51
7. REGISTER DESCRIPTIONS................................................................................................ 52
7.1
Register Configuration......................................................................................................................52
7.1.1
7.1.2
Big and Little Endian (the Bigend Bit)...............................................................................52
Configuration Bits for Backward Compatibility..................................................................53
7.2
7.3
Operating Mode Selection................................................................................................................54
Registers ..........................................................................................................................................55
7.3.1
PSRs (Program Status Registers)....................................................................................56
7.4
Exceptions........................................................................................................................................57
7.4.1
7.4.2
7.4.3
7.4.4
7.4.5
7.4.6
7.4.7
7.4.8
7.4.9
FIQ....................................................................................................................................57
IRQ ...................................................................................................................................58
Abort.................................................................................................................................58
Software Interrupt.............................................................................................................59
Undefined Instruction Trap................................................................................................60
Vector Summary...............................................................................................................60
Exception Priorities...........................................................................................................61
Interrupt Latencies............................................................................................................61
Reset ................................................................................................................................61
7.5
7.6
Configuration Control Registers .......................................................................................................62
7.5.1
7.5.2
7.5.3
Backward Compatibility ....................................................................................................62
Internal Coprocessor Instructions.....................................................................................62
Registers ..........................................................................................................................63
Register 1: Control (Write only) ........................................................................................................64
4
June 1997
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