CL-PS7500FE
System-on-a-Chip for Internet Appliance
10.3.21 T1low (0x50) — Timer 1 Low Bits.....................................................................................89
10.3.22 T1high (0x54) — Timer 1 High Bits ..................................................................................89
10.3.23 T1GO (0x58) — Timer 1 Go Command............................................................................90
10.3.24 T1LAT (0x5C) — Timer 1 Latch Command ......................................................................90
10.3.25 IRQSTC (0x60) — IRQ C Interrupts Status......................................................................90
10.3.26 IRQRQC (0x64) — IRQ C Interrupts Request..................................................................90
10.3.27 IRQMSKC (0x68) — IRQ C Interrupts Mask ....................................................................90
10.3.28 VIDMUX (0x6C) — Video LCD and Serial Sound MUX Control.......................................91
10.3.29 IRQSTD (0x70) — IRQ D Interrupts Status......................................................................91
10.3.30 IRQRQD (0x74) — IRQ D Interrupts Request..................................................................92
10.3.31 IRQMSKD (0x78) — IRQ D Interrupts Mask ....................................................................92
10.3.32 ROMCR1:0 (0x80 and 0x84) — ROM Control..................................................................93
10.3.33 REFCR (0x8C) — Refresh Period....................................................................................94
10.3.34 ID0 (0x94) — Chip ID Number (Low Byte) .......................................................................94
10.3.35 ID1 (0x98) — Chip ID Number (High Byte) ......................................................................94
10.3.36 VERSION (0x9C) — Chip Version Number ......................................................................94
10.3.37 MSEDAT (0xA8) — Mouse Data.......................................................................................94
10.3.38 MSECR (0xAC) — Mouse Control....................................................................................95
10.3.39 IOTCR (0xC4) — I/O Timing Control ................................................................................95
10.3.40 ECTCR (0xC8) — I/O Expansion Card Timing Control ....................................................95
10.3.41 ASTCR (0xCC) — I/O Asynchronous Timing Control.......................................................96
10.3.42 DRAMCR (0xD0) — DRAM Control .................................................................................96
10.3.43 SELFREF (0xD4) — DRAM Self-Refresh Control............................................................97
10.3.44 ATODICR (0xE0) — A-to-D Interrupt Control ...................................................................97
10.3.45 ATODSR (0xE4) — A-to-D Status ....................................................................................98
10.3.46 ATODCC (0xE8) — A-to-D Convertor Control..................................................................98
10.3.47 ATODCNT1 (0xEC) — A-to-D Counter 1..........................................................................99
10.3.48 ATODCNT2 (0xF0) — A-to-D Counter 2...........................................................................99
10.3.49 ATODCNT3 (0xF4) — A-to-D Counter 3...........................................................................99
10.3.50 ATODCNT4 (0xF8) — A-to-D Counter 4...........................................................................99
10.3.51 SDCURA (0x180) — Sound DMA Current A....................................................................99
10.3.52 SDENDA (0x184) — Sound DMA End A........................................................................100
10.3.53 SDCURB (0x188) — Sound DMA Current B..................................................................100
10.3.54 SDENDB (0x18C) — Sound DMA End B.......................................................................101
10.3.55 SDCR (0x190) — Sound DMA Control...........................................................................102
10.3.56 SDST (0x194) — Sound DMA Status.............................................................................102
10.3.57 CURSCUR (0x1C0) — Cursor DMA Current .................................................................103
10.3.58 CURSINIT (0x1C4) — Cursor DMA INIT........................................................................103
10.3.59 VIDCURB (0x1C8) — Duplex LCD Video DMA Current B .............................................103
10.3.60 VIDCURA (0x1D0) — Video DMA Current A..................................................................104
10.3.61 VIDEND (0x1D4) — Video DMA End .............................................................................104
10.3.62 VIDSTART (0x1D8) — Video DMA Start ........................................................................104
10.3.63 VIDINITA (0x1DC) — Video DMA INIT A........................................................................105
10.3.64 VIDCR (0x1E0) — Video DMA Control...........................................................................106
10.3.65 VIDINITB (0x1E8) — Duplex LCD Video DMA INIT B....................................................107
10.3.66 DMAST/DMARQ/DMAMSK (0x1F0,0x1F4,0x1F8) — DMA Interrupt Control................108
6
June 1997
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