CL-PS7500FE
System-on-a-Chip for Internet Appliance
7.7
Register 2: Level One Page Table (Write only) .................................................................................64
7.8
7.9
7.10
7.11
7.12
7.13
Register 3: Domain Access Control (Write only) ..............................................................................64
Register 4: Reserved........................................................................................................................64
Register 5: Fault Status/Translation Lookaside Buffer Flush ............................................................65
Register 6: Fault Address/TLB Purge ...............................................................................................65
Register 7: IDC Flush (Write only)....................................................................................................65
Registers 8–15: Reserved ................................................................................................................65
8. MEMORY MAP ......................................................................................................................66
9. MEMORY SUBSYSTEMS.....................................................................................................67
9.1
ROM Interface ..................................................................................................................................67
9.1.1 ROM Bank Configuration and Timing ...............................................................................68
DRAM Interface................................................................................................................................69
9.2
9.2.1
9.2.2
9.2.3
9.2.4
9.2.5
9.2.6
9.2.7
DRAM Control Registers ..................................................................................................69
DRAM Address Multiplexing............................................................................................70
Selection Between 16- and 32-bit DRAM .........................................................................70
EDO and Timing Mode Selection .....................................................................................71
DRAM Refresh..................................................................................................................72
DRAM Self-Refresh ..........................................................................................................73
Non-Sequential Access Time and RAS Precharge ..........................................................73
9.3
DMA Channels .................................................................................................................................74
9.3.1
9.3.2
9.3.3
9.3.4
Video DMA.......................................................................................................................74
Cursor DMA.....................................................................................................................75
Sound DMA .....................................................................................................................75
The Sound DMA State Machine .......................................................................................76
10. MEMORY AND I/O PROGRAMMERS’ MODEL...................................................................78
10.1
10.2
10.3
Introduction.......................................................................................................................................78
Register Summary............................................................................................................................78
Register Descriptions .......................................................................................................................81
10.3.1
10.3.2
10.3.3
10.3.4
10.3.5
10.3.6
10.3.7
10.3.8
10.3.9
IOCR (0x00) — I/O Control...............................................................................................81
KBDDAT (0x04) — Keyboard Data ...................................................................................81
KBDCR (0x08) — Keyboard Control.................................................................................82
IOLINES (0x0C) — IOP[7:0] Port Control.........................................................................83
IRQSTA (0x10) — IRQ A Interrupts Status.......................................................................83
IRQRQA (0x14) — IRQ A Interrupts Request/Clear.........................................................84
IRQMSKA (0x18) — IRQ A Interrupts Mask.....................................................................84
SUSMODE (0x1C) — SUSPEND Mode...........................................................................85
IRQSTB (0x20) — IRQ B Interrupts Status ......................................................................85
10.3.10 IRQRQB (0x24) — IRQ B Interrupts Request ..................................................................86
10.3.11 IRQMSKB (0x28) — IRQ B Interrupts Mask.....................................................................86
10.3.12 STOPMODE (0x2C) — STOP Mode ................................................................................87
10.3.13 FIQST (0x30) — FIQ Interrupts Status.............................................................................87
10.3.14 FIQRQ (0x34) — FIQ Interrupts Request.........................................................................87
10.3.15 FIQMSK (0x38) — FIQ Interrupts Mask ...........................................................................88
10.3.16 CLKCTL (0x3C) — Clock Control.....................................................................................88
10.3.17 T0low (0x40) — Timer 0 Low Bits.....................................................................................89
10.3.18 T0high (0x44) — Timer 0 High Bits...................................................................................89
10.3.19 T0GO (0x48) — Timer 0 Go Command............................................................................89
10.3.20 T0LAT (0x4C) — Timer 0 Latch Command.......................................................................89
June 1997
5
ADVANCE DATA BOOK v2.0
TABLE OF CONTENTS
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STM32H743技术深度剖析与应用案例探索
LM321中文资料解析：引脚功能介绍、技术特点、技术特性分析
74HC14芯片资料介绍：性能特性分析、引脚介绍
LM1875芯片手册：功放参数分析、引脚说明、电路设计要点
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