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CD74HCT297E PDF预览

CD74HCT297E

更新时间： 2024-11-19 22:40:23
品牌 Logo 应用领域
德州仪器 - TI 逻辑集成电路
页数 文件大小 规格书
11页 99K
描述
High-Speed CMOS Logic Digital Phase-Locked-Loop

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CD74HCT297E 技术参数

是否Rohs认证：符合生命周期：Active
零件包装代码：DIP包装说明：DIP-16
针数：16Reach Compliance Code：compliant
HTS代码：8542.39.00.01Factory Lead Time：1 week
风险等级：0.85Samacsys Confidence：3
Samacsys Status：ReleasedSamacsys PartID：181234
Samacsys Pin Count：16Samacsys Part Category：Integrated Circuit
Samacsys Package Category：Dual-In-Line PackagesSamacsys Footprint Name：N (R-PDIP-T16)
Samacsys Released Date：2015-06-25 00:00:00Is Samacsys：N
系列：HCTJESD-30 代码：R-PDIP-T16
JESD-609代码：e4长度：19.3 mm
逻辑集成电路类型：LOGIC CIRCUIT最大I（ol）：0.004 A
位数：1功能数量：1
端子数量：16最高工作温度：125 °C
最低工作温度：-55 °C封装主体材料：PLASTIC/EPOXY
封装代码：DIP封装形状：RECTANGULAR
封装形式：IN-LINE包装方法：TUBE
峰值回流温度（摄氏度）：NOT SPECIFIED最大电源电流（ICC）：0.08 mA
Prop。Delay @ Nom-Sup：50 ns传播延迟（tpd）：50 ns
认证状态：Not Qualified座面最大高度：5.08 mm
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：NO
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：THROUGH-HOLE
端子节距：2.54 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED宽度：6.35 mm
Base Number Matches：1

CD74HCT297E 数据手册

 浏览型号CD74HCT297E的Datasheet PDF文件第2页浏览型号CD74HCT297E的Datasheet PDF文件第3页浏览型号CD74HCT297E的Datasheet PDF文件第4页浏览型号CD74HCT297E的Datasheet PDF文件第5页浏览型号CD74HCT297E的Datasheet PDF文件第6页浏览型号CD74HCT297E的Datasheet PDF文件第7页 
CD74HC297,  
CD74HCT297  
Data sheet acquired from Harris Semiconductor  
SCHS177  
High-Speed CMOS Logic  
Digital Phase-Locked-Loop  
November 1997  
Features  
Description  
• Digital Design Avoids Analog Compensation Errors  
• Easily Cascadable for Higher Order Loops  
The Harris CD74HC297 and CD74HCT297 are high-speed  
silicon gate CMOS devices that are pin-compatible with low  
power Schottky TTL (LSTTL).  
[ /Title  
(CD74  
HC297  
,
CD74  
HCT29  
7)  
• Useful Frequency Range  
These devices are designed to provide a simple, cost-effec-  
tive solution to high-accuracy, digital, phase-locked-loop appli-  
cations. They contain all the necessary circuits, with the  
exception of the divide-by-N counter, to build first-order  
phase-locked-loops.  
- K-Clock . . . . . . . . . . . . . . . . . . . . . . . . . .DC to 55MHz (Typ)  
- I/D-Clock . . . . . . . . . . . . . . . . . . . . DC to 35MHz (Typ)  
• Dynamically Variable Bandwidth  
• Very Narrow Bandwidth Attainable  
• Power-On Reset  
Both EXCLUSIVE-OR (XORPD) and edge-controlled phase  
detectors (ECPD) are provided for maximum flexibility. The  
input signals for the EXCLUSIVE-OR phase detector must  
have a 50% duty factor to obtain the maximum lock-range.  
/Sub-  
ject  
• Output Capability  
- Standard. . . . . . . . . . . . . . . . . . . . XORPD  
, ECPD  
OUT  
OUT  
OUT  
(High-  
Speed  
CMOS  
Logic  
Digi-  
tal  
Proper partitioning of the loop function, with many of the build-  
ing blocks external to the package, makes it easy for the  
designer to incorporate ripple cancellation (see Figure 2) or to  
cascade to higher order phase-locked-loops.  
- Bus Driver . . . . . . . . . . . . . . . . . . . . . . . . . . . . . I/D  
• Fanout (Over Temperature Range)  
- Standard Outputs . . . . . . . . . . . . . . . . . . 10 LSTTL Loads  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads  
The length of the up/down K-counter is digitally programmable  
according to the K-counter function table. With A, B, C and D  
all LOW, the K-counter is disabled. With A HIGH and B, C and  
D LOW, the K-counter is only three stages long, which widens  
the bandwidth or capture range and shortens the lock time of  
the loop. When A, B, C and D are all programmed HIGH, the  
K-counter becomes seventeen stages long, which narrows  
the bandwidth or capture range and lengthens the lock time.  
Real-time control of loop bandwidth by manipulating the A to  
D inputs can maximize the overall performance of the digital  
phase-locked-loop.  
• Balanced Propagation Delay and Transition Times  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
Phase-  
Locked  
• CD74HC297 Types  
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 to 6V  
- High Noise ImmunityN = 30%, N = 30% of V at 5V  
IL IH CC  
• CD74HCT297 Types  
- Operation Voltage . . . . . . . . . . . . . . . . . . . . . . . . 4.5 to 5.5V  
- Direct LSTTL Input Logic Compatibility  
The CD74HC297 and CD74HCT297 can perform the classic  
first order phase-locked-loop function without using analog  
components. The accuracy of the digital phase-locked-loop  
V
= 0.8V (Max), V = 2V (Min)  
IH  
IL  
- CMOS Input Compatibility I ≤ 1µA at V , V  
OL OH  
I
(DPLL) is not affected by V  
depends solely on accuracies of the K-clock and loop propa-  
gation delays.  
and temperature variations but  
CC  
Ordering Information  
PKG.  
NO.  
o
PART NUMBER TEMP. RANGE ( C) PACKAGE  
CD74HC297E  
CD74HCT297E  
NOTES:  
-55 to 125  
-55 to 125  
16 Ld PDIP  
16 Ld PDIP  
E16.3  
E16.3  
Pinout  
CD74HC297, CD74HCT297 (PDIP)  
TOP VIEW  
1. When ordering, use the entire part number. Add the suffix 96 to  
obtain the variant in the tape and reel.  
B
A
1
2
3
4
5
6
7
8
16 V  
15 C  
14 D  
CC  
2. Wafer or die for this part number is available which meets all elec-  
trical specifications. Please contact your local sales office or  
Harris customer service for ordering information.  
EN  
CTR  
K
13 φA  
2
CP  
I/D  
12 ECPD  
OUT  
CP  
D/U  
11 XORPD  
OUT  
10 φB  
I/D  
OUT  
9
φA  
1
GND  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
File Number 1852.1  
Copyright © Harris Corporation 1997  
1
1234567...11

中文翻译

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CD74HCT297E 替代型号

型号 品牌 替代类型 描述 数据表
SN74LS297NE4 TI

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 DIGITAL PHASE-LOCKED-LOOP FILTERS
SN74LS297N TI

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 DIGITAL PHASE-LOCKED-LOOP FILTERS
CD74HCT297EE4 TI

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 High-Speed CMOS Logic Digital Phase-Locked Loop

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