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CD74HCT299M96G4 PDF预览

CD74HCT299M96G4

更新时间： 2024-11-20 05:28:07
品牌 Logo 应用领域
德州仪器 - TI 移位寄存器触发器逻辑集成电路光电二极管输出元件
页数 文件大小 规格书
17页 432K
描述
High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

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CD74HCT299M96G4 技术参数

是否无铅：不含铅是否Rohs认证：符合
生命周期：Active零件包装代码：SOIC
包装说明：SOIC-20针数：20
Reach Compliance Code：compliantHTS代码：8542.39.00.01
Factory Lead Time：6 weeks风险等级：5.35
Is Samacsys：N其他特性：COMMON I/O PINS; GATED OUTPUT CONTROL
计数方向：BIDIRECTIONAL系列：HCT
JESD-30 代码：R-PDSO-G20JESD-609代码：e4
长度：12.8 mm负载电容（CL）：50 pF
逻辑集成电路类型：PARALLEL IN PARALLEL OUT最大频率@ Nom-Sup：16000000 Hz
最大I（ol）：0.004 A湿度敏感等级：1
位数：8功能数量：1
端子数量：20最高工作温度：125 °C
最低工作温度：-55 °C输出特性：3-STATE
输出极性：TRUE封装主体材料：PLASTIC/EPOXY
封装代码：SOP封装等效代码：SOP20,.4
封装形状：RECTANGULAR封装形式：SMALL OUTLINE
包装方法：TR峰值回流温度（摄氏度）：260
电源：2/6 V最大电源电流（ICC）：0.08 mA
Prop。Delay @ Nom-Sup：56 ns传播延迟（tpd）：68 ns
认证状态：Not Qualified施密特触发器：No
座面最大高度：2.65 mm子类别：Shift Registers
最大供电电压 (Vsup)：5.5 V最小供电电压 (Vsup)：4.5 V
标称供电电压 (Vsup)：5 V表面贴装：YES
技术：CMOS温度等级：MILITARY
端子面层：Nickel/Palladium/Gold (Ni/Pd/Au)端子形式：GULL WING
端子节距：1.27 mm端子位置：DUAL
处于峰值回流温度下的最长时间：NOT SPECIFIED触发器类型：POSITIVE EDGE
宽度：7.5 mm最小 fmax：16 MHz
Base Number Matches：1

CD74HCT299M96G4 数据手册

 浏览型号CD74HCT299M96G4的Datasheet PDF文件第2页浏览型号CD74HCT299M96G4的Datasheet PDF文件第3页浏览型号CD74HCT299M96G4的Datasheet PDF文件第4页浏览型号CD74HCT299M96G4的Datasheet PDF文件第5页浏览型号CD74HCT299M96G4的Datasheet PDF文件第6页浏览型号CD74HCT299M96G4的Datasheet PDF文件第7页 
CD54HC299, CD74HC299,  
CD54HCT299, CD74HCT299  
Data sheet acquired from Harris Semiconductor  
SCHS178C  
High-Speed CMOS Logic  
8-Bit Universal Shift Register; Three-State  
January 1998 - Revised May 2003  
Features  
Description  
The ’HC259 and ’HCT299 are 8-bit shift/storage registers  
with three-state bus interface capability. The register has four  
synchronous-operating modes controlled by the two select  
inputs as shown in the mode select (S0, S1) table. The mode  
• Buffered Inputs  
• Four Operating Modes: Shift Left, Shift Right, Load  
and Store  
[ /Title  
(CD74  
HC299  
,
CD74  
HCT29  
9)  
select, the serial data (DS0, DS7) and the parallel data (I/O  
0
• Can be Cascaded for N-Bit Word Lengths  
- I/O ) respond only to the low-to-high transition of the clock  
7
(CP) pulse. S0, S1 and data inputs must be stable one set-  
up time prior to the clock positive transition.  
• I/O - I/O Bus Drive Capability and Three-State for  
0
7
Bus Oriented Applications  
o
The Master Reset (MR) is an asynchronous active low input.  
When MR output is low, the register is cleared regardless of  
the status of all other inputs. The register can be expanded  
by cascading same units by tying the serial output (Q0) to  
• Typical f = 50MHz at V  
= 5V, C = 15pF, T = 25 C  
MAX CC  
L
A
• Fanout (Over Temperature Range)  
- Standard Outputs. . . . . . . . . . . . . . . 10 LSTTL Loads  
/Sub-  
ject  
- Bus Driver Outputs . . . . . . . . . . . . . 15 LSTTL Loads the serial data (DS7) input of the preceding register, and  
tying the serial output (Q7) to the serial data (DS0) input of  
(High  
Speed  
CMOS  
Logic  
8-Bit  
Uni-  
o
o
• Wide Operating Temperature Range . . . -55 C to 125 C  
• Balanced Propagation Delay and Transition Times  
the following register. Recirculating the (n x 8) bits is  
accomplished by tying the Q7 of the last stage to the DS0 of  
the first stage.  
• Significant Power Reduction Compared to LSTTL  
Logic ICs  
The three-state input/output I(/O) port has three modes of  
operation:  
• HC Types  
1. Both output enable (OE1 and OE2) inputs are low and S0  
or S1 or both are low, the data in the register is presented  
at the eight outputs.  
- 2V to 6V Operation  
versal  
Shift  
- High Noise Immunity: N = 30%, N = 30% of V  
IL IH CC  
at V  
= 5V  
CC  
2. When both S0 and S1 are high, I/O terminals are in the  
high impedance state but being input ports, ready for par-  
allel data to be loaded into eight registers with one clock  
transition regardless of the status of OE1 and OE2.  
• HCT Types  
- 4.5V to 5.5V Operation  
- Direct LSTTL Input Logic Compatibility,  
V = 0.8V (Max), V = 2V (Min)  
IL IH  
3. Either one of the two output enable inputs being high will  
force I/O terminals to be in the off-state. It is noted that  
each I/O terminal is a three-state output and a CMOS  
buffer input.  
- CMOS Input Compatibility, I ≤ 1µA at V , V  
l
OL OH  
Pinout  
Ordering Information  
CD54HC299, CD54HCT299  
(CERDIP)  
CD74HC299, CD74HCT299  
(PDIP, SOIC)  
o
PART NUMBER  
CD54HC299F3A  
CD54HCT299F3A  
CD74HC299E  
TEMP. RANGE ( C)  
-55 to 125  
PACKAGE  
20 Ld CERDIP  
20 Ld CERDIP  
20 Ld PDIP  
20 Ld SOIC  
20 Ld SOIC  
20 Ld PDIP  
20 Ld SOIC  
20 Ld SOIC  
TOP VIEW  
-55 to 125  
1
2
3
4
5
6
7
8
9
V
S0  
OE1  
OE2  
20  
19  
CC  
-55 to 125  
S1  
CD74HC299M  
-55 to 125  
18 DS7  
17 Q7  
CD74HC299M96  
CD74HCT299E  
CD74HCT299M  
CD74HCT299M96  
-55 to 125  
I/O  
6
I/O  
4
16 I/O  
7
-55 to 125  
I/O  
2
15 I/O  
5
-55 to 125  
I/O  
0
14 I/O  
3
-55 to 125  
Q0  
13 I/O  
12  
1
NOTE: When ordering, use the entire part number. The suffix 96  
denotes tape and reel.  
MR  
CP  
GND 10  
11 DS0  
CAUTION: These devices are sensitive to electrostatic discharge. Users should follow proper IC Handling Procedures.  
Copyright © 2003, Texas Instruments Incorporated  
1
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CD74HCT299M96G4 替代型号

型号 品牌 替代类型 描述 数据表
CD74HCT299MG4 TI

完全替代

 High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M TI

完全替代

 High Speed CMOS Logic 8-Bit Universal Shift Register; Three-State
CD74HCT299M96 TI

完全替代

 High-Speed CMOS Logic 8-Bit Universal Shift Register; Three-State

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